hbm_ctrl.hh

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/*
 * Copyright (c) 2022 The Regents of the University of California
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __HBM_CTRL_HH__
#define __HBM_CTRL_HH__
 
#include <deque>
#include <string>
#include <unordered_set>
#include <utility>
#include <vector>
 
#include "mem/mem_ctrl.hh"
#include "params/HBMCtrl.hh"
 
namespace gem5
{
 
namespace memory
{
 
class MemInterface;
class DRAMInterface;
 
 
class HBMCtrl : public MemCtrl
{
 
  protected:
 
    bool respQEmpty() override
    {
        return (respQueue.empty() && respQueuePC1.empty());
    }
 
  private:
 
    bool retryRdReqPC1;
    bool retryWrReqPC1;
 
    void pruneBurstTick() override;
 
  public:
    HBMCtrl(const HBMCtrlParams &p);
 
    void pruneRowBurstTick();
    void pruneColBurstTick();
 
    Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst,
                        bool row_cmd) override;
 
    Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
                        Tick max_multi_cmd_split = 0) override;
 
    EventFunctionWrapper nextReqEventPC1;
    EventFunctionWrapper respondEventPC1;
 
    bool readQueueFullPC0(unsigned int pkt_count) const;
    bool readQueueFullPC1(unsigned int pkt_count) const;
    bool readQueueFull(unsigned int pkt_count) const;
 
    bool writeQueueFullPC0(unsigned int pkt_count) const;
    bool writeQueueFullPC1(unsigned int pkt_count) const;
 
    uint64_t readQueueSizePC0 = 0;
    uint64_t readQueueSizePC1 = 0;
    uint64_t writeQueueSizePC0 = 0;
    uint64_t writeQueueSizePC1 = 0;
 
    std::deque<MemPacket*> respQueuePC1;
 
    std::unordered_multiset<Tick> rowBurstTicks;
 
    std::unordered_multiset<Tick> colBurstTicks;
 
    DRAMInterface* pc0Int;
    DRAMInterface* pc1Int;
 
    bool partitionedQ;
 
  public:
 
    bool respondEventPC1Scheduled() const
    {
        return respondEventPC1.scheduled();
    }
 
    bool requestEventScheduled(uint8_t pseudo_channel) const override
    {
        if (pseudo_channel == 0) {
            return MemCtrl::requestEventScheduled(pseudo_channel);
        } else {
            assert(pseudo_channel == 1);
            return nextReqEventPC1.scheduled();
        }
    }
 
    void restartScheduler(Tick tick, uint8_t pseudo_channel) override
    {
        if (pseudo_channel == 0) {
            MemCtrl::restartScheduler(tick);
        } else {
            schedule(nextReqEventPC1, tick);
        }
    }
 
 
    virtual void init() override;
    virtual void startup() override;
    virtual void drainResume() override;
 
 
  protected:
    Tick recvAtomic(PacketPtr pkt) override;
    Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override;
    void recvFunctional(PacketPtr pkt) override;
    bool recvTimingReq(PacketPtr pkt) override;
 
};
 
} // namespace memory
} // namespace gem5
 
#endif //__HBM_CTRL_HH__