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malta_cchip.hh
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28 
33 #ifndef __MALTA_CCHIP_HH__
34 #define __MALTA_CCHIP_HH__
35 
36 #include "dev/mips/malta.hh"
37 #include "dev/io_device.hh"
38 #include "params/MaltaCChip.hh"
39 
40 namespace gem5
41 {
42 
47 class MaltaCChip : public BasicPioDevice
48 {
49  protected:
56 
61  //uint64_t dim[Malta::Max_CPUs];
62 
67  //uint64_t dir[Malta::Max_CPUs];
68 
73  //uint64_t drir;
74 
76  //uint64_t ipint;
77 
79  //uint64_t itint;
80 
81  public:
82  using Params = MaltaCChipParams;
83 
89  MaltaCChip(const Params &p);
90 
91  Tick read(PacketPtr pkt) override;
92 
93  Tick write(PacketPtr pkt) override;
94 
98  void postRTC();
99 
104  void postIntr(uint32_t interrupt);
105 
110  void clearIntr(uint32_t interrupt);
111 
116  void clearIPI(uint64_t ipintr);
117 
122  void clearITI(uint64_t itintr);
123 
128  void reqIPI(uint64_t ipreq);
129 
130  void serialize(CheckpointOut &cp) const override;
131  void unserialize(CheckpointIn &cp) override;
132 };
133 
134 } // namespace gem5
135 
136 #endif // __MALTA_CCHIP_HH__
io_device.hh
gem5::Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:54
malta.hh
gem5::MaltaCChip::postIntr
void postIntr(uint32_t interrupt)
post an interrupt to the CPU.
Definition: malta_cchip.cc:104
gem5::MaltaCChip::clearITI
void clearITI(uint64_t itintr)
clear a timer interrupt previously posted to the CPU.
Definition: malta_cchip.cc:85
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MaltaCChip::clearIntr
void clearIntr(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Definition: malta_cchip.cc:120
gem5::MaltaCChip
Malta CChip CSR Emulation.
Definition: malta_cchip.hh:47
gem5::MaltaCChip::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:72
gem5::MaltaCChip::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_cchip.cc:137
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::MaltaCChip::MaltaCChip
MaltaCChip(const Params &p)
Initialize the Malta CChip by setting all of the device register to 0.
Definition: malta_cchip.cc:54
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::MaltaCChip::reqIPI
void reqIPI(uint64_t ipreq)
request an interrupt be posted to the CPU.
Definition: malta_cchip.cc:91
gem5::MaltaCChip::malta
Malta * malta
pointer to the malta object.
Definition: malta_cchip.hh:55
gem5::MaltaCChip::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:65
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MaltaCChip::postRTC
void postRTC()
post an RTC interrupt to the CPU
Definition: malta_cchip.cc:98
gem5::MaltaCChip::clearIPI
void clearIPI(uint64_t ipintr)
post an ipi interrupt to the CPU.
Definition: malta_cchip.cc:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::MaltaCChip::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_cchip.cc:142

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