mem_interface.hh

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/*
 * Copyright (c) 2012-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Amin Farmahini-Farahani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __MEM_INTERFACE_HH__
#define __MEM_INTERFACE_HH__
 
#include <deque>
#include <string>
#include <unordered_set>
#include <utility>
#include <vector>
 
#include "base/compiler.hh"
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/PageManage.hh"
#include "mem/abstract_mem.hh"
#include "mem/mem_ctrl.hh"
#include "params/MemInterface.hh"
#include "sim/eventq.hh"
 
namespace gem5
{
 
namespace memory
{
 
class MemInterface : public AbstractMemory
{
  protected:
    class Bank
    {
 
      public:
        static const uint32_t NO_ROW = -1;
 
        uint32_t openRow;
        uint8_t bank;
        uint8_t bankgr;
 
        Tick rdAllowedAt;
        Tick wrAllowedAt;
        Tick preAllowedAt;
        Tick actAllowedAt;
 
        uint32_t rowAccesses;
        uint32_t bytesAccessed;
 
        Bank() :
            openRow(NO_ROW), bank(0), bankgr(0),
            rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
            rowAccesses(0), bytesAccessed(0)
        { }
    };
 
    MemCtrl* ctrl;
 
    unsigned int maxCommandsPerWindow;
 
    enums::AddrMap addrMapping;
 
    const uint32_t burstSize;
    const uint32_t deviceSize;
    const uint32_t deviceRowBufferSize;
    const uint32_t devicesPerRank;
    const uint32_t rowBufferSize;
    const uint32_t burstsPerRowBuffer;
    const uint32_t burstsPerStripe;
    const uint32_t ranksPerChannel;
    const uint32_t banksPerRank;
    uint32_t rowsPerBank;
 
    GEM5_CLASS_VAR_USED const Tick tCK;
    const Tick tCS;
    const Tick tBURST;
    const Tick tRTW;
    const Tick tWTR;
 
    /*
     * @return delay between write and read commands
     */
    virtual Tick writeToReadDelay() const { return tBURST + tWTR; }
 
    /*
     * @return delay between write and read commands
     */
    Tick readToWriteDelay() const { return tBURST + tRTW; }
 
    /*
     * @return delay between accesses to different ranks
     */
    Tick rankToRankDelay() const { return tBURST + tCS; }
 
  public:
 
    const uint32_t readBufferSize;
    const uint32_t writeBufferSize;
 
    uint32_t numWritesQueued;
 
    Tick nextBurstAt = 0;
    Tick nextReqTime = 0;
 
    uint8_t pseudoChannel;
 
    void setCtrl(MemCtrl* _ctrl, unsigned int command_window,
                                    uint8_t pseudo_channel = 0);
 
    Addr getCtrlAddr(Addr addr) { return range.getOffset(addr); }
 
    virtual void setupRank(const uint8_t rank, const bool is_read) = 0;
 
    virtual bool allRanksDrained() const = 0;
 
    virtual std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
 
    /*
     * Function to calulate unloaded latency
     */
    virtual Tick accessLatency() const = 0;
 
    uint32_t bytesPerBurst() const { return burstSize; }
 
    /*
     * @return time to offset next command
     */
    virtual Tick commandOffset() const = 0;
 
    virtual bool burstReady(MemPacket* pkt) const = 0;
 
    Tick rankDelay() const { return tCS; }
 
    Tick minReadToWriteDataGap() const { return std::min(tRTW, tCS); }
 
    Tick minWriteToReadDataGap() const { return std::min(tWTR, tCS); }
 
    virtual MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
                           unsigned int size, bool is_read,
                           uint8_t pseudo_channel = 0)
    {
        panic("MemInterface decodePacket should not be executed from here.\n");
        return nullptr;
    }
 
    virtual void addRankToRankDelay(Tick cmd_at) = 0;
 
    virtual bool isBusy(bool read_queue_empty, bool all_writes_nvm) = 0;
 
    virtual std::pair<Tick, Tick>
    doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
                  const std::vector<MemPacketQueue>& queue) = 0;
 
    virtual void respondEvent(uint8_t rank)
    {
        panic("MemInterface respondEvent should not be executed from here.\n");
    };
 
    virtual void checkRefreshState(uint8_t rank)
    {
        panic("MemInterface checkRefreshState (DRAM) should "
        "not be executed from here.\n");
    };
 
    virtual void drainRanks()
    {
        panic("MemInterface drainRanks (DRAM) should "
        "not be executed from here.\n");
    }
 
    virtual void suspend()
    {
        panic("MemInterface suspend (DRAM) should "
        "not be executed from here.\n");
    }
 
    virtual bool readsWaitingToIssue() const
    {
        panic("MemInterface readsWaitingToIssue (NVM) "
        "should not be executed from here.\n");
    };
 
    virtual void chooseRead(MemPacketQueue& queue)
    {
        panic("MemInterface chooseRead (NVM) should "
        "not be executed from here.\n");
    };
 
    virtual bool writeRespQueueFull() const
    {
        panic("MemInterface writeRespQueueFull (NVM) "
        "should not be executed from here.\n");
    }
 
    typedef MemInterfaceParams Params;
    MemInterface(const Params &_p);
};
 
 
} // namespace memory
} // namespace gem5
 
#endif //__MEM_INTERFACE_HH__