gem5
v22.0.0.1
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cpu
minor
activity.cc
Go to the documentation of this file.
1
/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
6
* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
9
* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
16
* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
21
* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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38
#include "
cpu/minor/activity.hh
"
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#include <sstream>
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#include "
cpu/minor/trace.hh
"
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namespace
gem5
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{
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GEM5_DEPRECATED_NAMESPACE
(Minor,
minor
);
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namespace
minor
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{
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void
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MinorActivityRecorder::minorTrace
()
const
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{
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std::ostringstream stages;
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unsigned
int
num_stages =
getNumStages
();
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unsigned
int
stage_index = 0;
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while
(stage_index < num_stages) {
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stages << (
getStageActive
(stage_index) ?
'1'
:
'E'
);
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stage_index++;
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if
(stage_index != num_stages)
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stages <<
','
;
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}
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minor::minorTrace
(
"activity=%d stages=%s\n"
,
getActivityCount
(),
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stages.str());
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}
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}
// namespace minor
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}
// namespace gem5
minor
gem5::ActivityRecorder::getActivityCount
int getActivityCount() const
Returns how many things are active within the recorder.
Definition:
activity.hh:82
gem5::minor::MinorActivityRecorder::minorTrace
void minorTrace() const
Definition:
activity.cc:52
gem5::ActivityRecorder::getNumStages
int getNumStages() const
Returns the number of stages.
Definition:
activity.hh:79
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::minorTrace
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Definition:
trace.hh:67
gem5::ActivityRecorder::getStageActive
bool getStageActive(const int idx) const
Returns the activity status of a stage.
Definition:
activity.hh:76
trace.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
activity.hh
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