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cc.hh
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37 
38 #ifndef __ARCH_ARM_REGS_CC_HH__
39 #define __ARCH_ARM_REGS_CC_HH__
40 
41 #include "cpu/reg_class.hh"
42 #include "debug/CCRegs.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA
48 {
49 
50 namespace cc_reg
51 {
52 
53 enum : RegIndex
54 {
55  _NzIdx,
56  _CIdx,
57  _VIdx,
58  _GeIdx,
59  _FpIdx,
60  _ZeroIdx,
61  NumRegs
62 };
63 
64 } // namespace cc_reg
65 
66 inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
67  cc_reg::NumRegs, debug::CCRegs);
68 
69 namespace cc_reg
70 {
71 
72 inline constexpr RegId
73  Nz = ccRegClass[_NzIdx],
74  C = ccRegClass[_CIdx],
75  V = ccRegClass[_VIdx],
76  Ge = ccRegClass[_GeIdx],
77  Fp = ccRegClass[_FpIdx],
78  Zero = ccRegClass[_ZeroIdx];
79 
80 const char * const RegName[NumRegs] = {
81  "nz",
82  "c",
83  "v",
84  "ge",
85  "fp",
86  "zero"
87 };
88 
89 } // namespace cc_reg
90 
91 enum ConditionCode
92 {
93  COND_EQ = 0,
94  COND_NE, // 1
95  COND_CS, // 2
96  COND_CC, // 3
97  COND_MI, // 4
98  COND_PL, // 5
99  COND_VS, // 6
100  COND_VC, // 7
101  COND_HI, // 8
102  COND_LS, // 9
103  COND_GE, // 10
104  COND_LT, // 11
105  COND_GT, // 12
106  COND_LE, // 13
107  COND_AL, // 14
108  COND_UC // 15
109 };
110 
111 } // namespace ArmISA
112 } // namespace gem5
113 
114 #endif // __ARCH_ARM_REGS_CC_HH__
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:61
gem5::ArmISA::cc_reg::_CIdx
@ _CIdx
Definition: cc.hh:56
gem5::ArmISA::cc_reg::_GeIdx
@ _GeIdx
Definition: cc.hh:58
gem5::ArmISA::cc_reg::_NzIdx
@ _NzIdx
Definition: cc.hh:55
gem5::ArmISA::cc_reg::_VIdx
@ _VIdx
Definition: cc.hh:57
gem5::ArmISA::cc_reg::_ZeroIdx
@ _ZeroIdx
Definition: cc.hh:60
gem5::ArmISA::cc_reg::_FpIdx
@ _FpIdx
Definition: cc.hh:59
gem5::ArmISA::cc_reg::V
constexpr RegId V
Definition: cc.hh:75
gem5::ArmISA::cc_reg::C
constexpr RegId C
Definition: cc.hh:74
gem5::ArmISA::cc_reg::Fp
constexpr RegId Fp
Definition: cc.hh:77
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge
Definition: cc.hh:76
gem5::ArmISA::cc_reg::RegName
const char *const RegName[NumRegs]
Definition: cc.hh:80
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero
Definition: cc.hh:78
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz
Definition: cc.hh:73
gem5::ArmISA::ccRegClass
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:92
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:93
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:98
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:97
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:103
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:102
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:106
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:100
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:101
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:96
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:105
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:108
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:94
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:99
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:104
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:107
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:95
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:38
gem5::CCRegClassName
constexpr char CCRegClassName[]
Definition: reg_class.hh:78
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:67
reg_class.hh
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