isa.hh

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/*
 * Copyright (c) 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright 2020 Google Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_GENERIC_ISA_HH__
#define __ARCH_GENERIC_ISA_HH__
 
#include <vector>
 
#include "arch/generic/pcstate.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class ThreadContext;
class ExecContext;
 
class BaseISA : public SimObject
{
  public:
    typedef std::vector<const RegClass *> RegClasses;
 
  protected:
    using SimObject::SimObject;
 
    ThreadContext *tc = nullptr;
 
    RegClasses _regClasses;
 
  public:
    virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
    virtual void clear() {}
    virtual void clearLoadReservation(ContextID cid) {}
 
    virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
    virtual RegVal readMiscReg(RegIndex idx) = 0;
 
    virtual void setMiscRegNoEffect(RegIndex idx, RegVal val) = 0;
    virtual void setMiscReg(RegIndex idx, RegVal val) = 0;
 
    virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
    virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
 
    virtual uint64_t getExecutingAsid() const { return 0; }
    virtual bool inUserMode() const = 0;
    virtual void copyRegsFrom(ThreadContext *src) = 0;
 
    virtual void resetThread() { panic("Thread reset not implemented."); }
 
    const RegClasses &regClasses() const { return _regClasses; }
 
    // Locked memory handling functions.
    virtual void handleLockedRead(const RequestPtr &req) {}
    virtual void
    handleLockedRead(ExecContext *xc, const RequestPtr &req)
    {
        handleLockedRead(req);
    }
    virtual bool
    handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
    {
        return true;
    }
    virtual bool
    handleLockedWrite(ExecContext *xc, const RequestPtr &req,
            Addr cacheBlockMask)
    {
        return handleLockedWrite(req, cacheBlockMask);
    }
 
    virtual void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) {}
    virtual void
    handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
    {
        handleLockedSnoop(pkt, cacheBlockMask);
    }
    virtual void handleLockedSnoopHit() {}
    virtual void
    handleLockedSnoopHit(ExecContext *xc)
    {
        handleLockedSnoopHit();
    }
 
    virtual void globalClearExclusive() {}
    virtual void
    globalClearExclusive(ExecContext *xc)
    {
        globalClearExclusive();
    }
};
 
} // namespace gem5
 
#endif // __ARCH_GENERIC_ISA_HH__