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mem
qos
policy.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
7
* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
16
* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
18
* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
21
* neither the name of the copyright holders nor the names of its
22
* contributors may be used to endorse or promote products derived from
23
* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
mem/qos/policy.hh
"
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#include "params/QoSPolicy.hh"
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namespace
gem5
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{
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namespace
memory
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{
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namespace
qos
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{
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Policy::Policy
(
const
Params
&
p
)
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:
SimObject
(
p
)
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{}
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Policy::~Policy
() {}
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uint8_t
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Policy::schedule
(
const
PacketPtr
pkt)
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{
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assert(pkt->
req
);
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return
schedule
(pkt->
req
->requestorId(), pkt->
getSize
());
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}
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}
// namespace qos
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}
// namespace memory
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}
// namespace gem5
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition
packet.hh:295
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition
packet.hh:377
gem5::Packet::getSize
unsigned getSize() const
Definition
packet.hh:817
gem5::SimObject
Abstract superclass for simulation objects.
Definition
sim_object.hh:148
gem5::memory::qos::Policy::schedule
virtual uint8_t schedule(const RequestorID requestor_id, const uint64_t data)=0
Schedules data - must be defined by derived class.
gem5::memory::qos::Policy::Policy
Policy(const Params &p)
Definition
policy.cc:51
gem5::memory::qos::Policy::~Policy
virtual ~Policy()
Definition
policy.cc:55
gem5::memory::qos::Policy::Params
QoSPolicyParams Params
Definition
policy.hh:73
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition
gpu_translation_state.hh:38
policy.hh
memory
Definition
mem.h:38
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