gem5 [DEVELOP-FOR-25.0]
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amdgpu_vm.hh File Reference
#include <vector>
#include "arch/amdgpu/vega/pagetable_walker.hh"
#include "base/intmath.hh"
#include "dev/amdgpu/amdgpu_defines.hh"
#include "mem/packet.hh"
#include "mem/translation_gen.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Classes

class  gem5::AMDGPUVM
 
struct  gem5::AMDGPUVM::GEM5_PACKED
 
struct  gem5::AMDGPUVM::AMDGPUSysVMContext
 
class  gem5::AMDGPUVM::AGPTranslationGen
 Translation range generators. More...
 
class  gem5::AMDGPUVM::GARTTranslationGen
 
class  gem5::AMDGPUVM::MMHUBTranslationGen
 
class  gem5::AMDGPUVM::UserTranslationGen
 

Namespaces

namespace  gem5
 Copyright (c) 2024 Arm Limited All rights reserved.
 

Macros

#define mmVM_INVALIDATE_ENG17_ACK   0x08c6
 MMIO offsets for graphics register bus manager (GRBM).
 
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32   0x08eb
 
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32   0x08ec
 
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32   0x090b
 
#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32   0x090c
 
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32   0x092b
 
#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32   0x092c
 
#define MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32   0x08cb
 
#define MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32   0x08cc
 
#define MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_LO32   0x08eb
 
#define MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_HI32   0x08ec
 
#define MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_LO32   0x090b
 
#define MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_HI32   0x090c
 
#define mmMC_VM_FB_OFFSET   0x096b
 
#define mmMC_VM_FB_LOCATION_BASE   0x0980
 
#define mmMC_VM_FB_LOCATION_TOP   0x0981
 
#define mmMC_VM_AGP_TOP   0x0982
 
#define mmMC_VM_AGP_BOT   0x0983
 
#define mmMC_VM_AGP_BASE   0x0984
 
#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR   0x0985
 
#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR   0x0986
 
#define MI300X_VM_FB_OFFSET   0x0947
 
#define MI300X_VM_FB_LOCATION_BASE   0x095c
 
#define MI300X_VM_FB_LOCATION_TOP   0x095d
 
#define MI300X_VM_AGP_TOP   0x095e
 
#define MI300X_VM_AGP_BOT   0x095f
 
#define MI300X_VM_AGP_BASE   0x0960
 
#define MI300X_VM_SYSTEM_APERTURE_LOW_ADDR   0x0961
 
#define MI300X_VM_SYSTEM_APERTURE_HIGH_ADDR   0x0962
 
#define mmMMHUB_VM_INVALIDATE_ENG17_SEM   0x06e2
 
#define mmMMHUB_VM_INVALIDATE_ENG17_REQ   0x06f4
 
#define mmMMHUB_VM_INVALIDATE_ENG17_ACK   0x0706
 
#define mmMMHUB_VM_FB_LOCATION_BASE   0x082c
 
#define mmMMHUB_VM_FB_LOCATION_TOP   0x082d
 
#define VEGA10_FB_LOCATION_BASE   0x6a0b0
 
#define VEGA10_FB_LOCATION_TOP   0x6a0b4
 
#define MI100_MEM_SIZE_REG   0x0378c
 
#define MI100_FB_LOCATION_BASE   0x6ac00
 
#define MI100_FB_LOCATION_TOP   0x6ac04
 
#define MI200_MEM_SIZE_REG   0x0378c
 
#define MI200_FB_LOCATION_BASE   0x6b300
 
#define MI200_FB_LOCATION_TOP   0x6b304
 
#define MI300X_MEM_SIZE_REG   0x0378c
 
#define MI300X_FB_LOCATION_BASE   0x63270
 
#define MI300X_FB_LOCATION_TOP   0x63274
 
#define MI300X_VM_INVALIDATE_ENG17_ACK   0x08a6
 

Enumerations

enum  gem5::mmio_range_t : int {
  gem5::NBIO_MMIO_RANGE , gem5::MMHUB_MMIO_RANGE , gem5::GFX_MMIO_RANGE , gem5::GRBM_MMIO_RANGE ,
  gem5::IH_MMIO_RANGE , gem5::NUM_MMIO_RANGES
}
 

Variables

static constexpr int AMDGPU_VM_COUNT = 16
 
static constexpr int AMDGPU_AGP_PAGE_SIZE = 4096
 
static constexpr int AMDGPU_GART_PAGE_SIZE = 4096
 
static constexpr int AMDGPU_MMHUB_PAGE_SIZE = 4096
 
static constexpr int AMDGPU_USER_PAGE_SIZE = 4096
 

Macro Definition Documentation

◆ MI100_FB_LOCATION_BASE

#define MI100_FB_LOCATION_BASE   0x6ac00

Definition at line 97 of file amdgpu_vm.hh.

◆ MI100_FB_LOCATION_TOP

#define MI100_FB_LOCATION_TOP   0x6ac04

Definition at line 98 of file amdgpu_vm.hh.

◆ MI100_MEM_SIZE_REG

#define MI100_MEM_SIZE_REG   0x0378c

Definition at line 96 of file amdgpu_vm.hh.

◆ MI200_FB_LOCATION_BASE

#define MI200_FB_LOCATION_BASE   0x6b300

Definition at line 101 of file amdgpu_vm.hh.

◆ MI200_FB_LOCATION_TOP

#define MI200_FB_LOCATION_TOP   0x6b304

Definition at line 102 of file amdgpu_vm.hh.

◆ MI200_MEM_SIZE_REG

#define MI200_MEM_SIZE_REG   0x0378c

Definition at line 100 of file amdgpu_vm.hh.

◆ MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32

#define MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32   0x08cc

Definition at line 63 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32

#define MI300X_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32   0x08cb

Definition at line 62 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_HI32

#define MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_HI32   0x090c

Definition at line 67 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_LO32

#define MI300X_CONTEXT0_PAGE_TABLE_END_ADDR_LO32   0x090b

Definition at line 66 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_HI32

#define MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_HI32   0x08ec

Definition at line 65 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_LO32

#define MI300X_CONTEXT0_PAGE_TABLE_START_ADDR_LO32   0x08eb

Definition at line 64 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_FB_LOCATION_BASE

#define MI300X_FB_LOCATION_BASE   0x63270

Definition at line 105 of file amdgpu_vm.hh.

◆ MI300X_FB_LOCATION_TOP

#define MI300X_FB_LOCATION_TOP   0x63274

Definition at line 106 of file amdgpu_vm.hh.

◆ MI300X_MEM_SIZE_REG

#define MI300X_MEM_SIZE_REG   0x0378c

Definition at line 104 of file amdgpu_vm.hh.

◆ MI300X_VM_AGP_BASE

#define MI300X_VM_AGP_BASE   0x0960

Definition at line 83 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_AGP_BOT

#define MI300X_VM_AGP_BOT   0x095f

Definition at line 82 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_AGP_TOP

#define MI300X_VM_AGP_TOP   0x095e

Definition at line 81 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_FB_LOCATION_BASE

#define MI300X_VM_FB_LOCATION_BASE   0x095c

Definition at line 79 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_FB_LOCATION_TOP

#define MI300X_VM_FB_LOCATION_TOP   0x095d

Definition at line 80 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_FB_OFFSET

#define MI300X_VM_FB_OFFSET   0x0947

Definition at line 78 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_INVALIDATE_ENG17_ACK

#define MI300X_VM_INVALIDATE_ENG17_ACK   0x08a6

Definition at line 107 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ MI300X_VM_SYSTEM_APERTURE_HIGH_ADDR

#define MI300X_VM_SYSTEM_APERTURE_HIGH_ADDR   0x0962

Definition at line 85 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ MI300X_VM_SYSTEM_APERTURE_LOW_ADDR

#define MI300X_VM_SYSTEM_APERTURE_LOW_ADDR   0x0961

Definition at line 84 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx940().

◆ mmMC_VM_AGP_BASE

#define mmMC_VM_AGP_BASE   0x0984

Definition at line 74 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_AGP_BOT

#define mmMC_VM_AGP_BOT   0x0983

Definition at line 73 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_AGP_TOP

#define mmMC_VM_AGP_TOP   0x0982

Definition at line 72 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_FB_LOCATION_BASE

#define mmMC_VM_FB_LOCATION_BASE   0x0980

Definition at line 70 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_FB_LOCATION_TOP

#define mmMC_VM_FB_LOCATION_TOP   0x0981

Definition at line 71 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_FB_OFFSET

#define mmMC_VM_FB_OFFSET   0x096b

Definition at line 69 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR

#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR   0x0986

Definition at line 76 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMC_VM_SYSTEM_APERTURE_LOW_ADDR

#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR   0x0985

Definition at line 75 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmMMHUB_VM_FB_LOCATION_BASE

#define mmMMHUB_VM_FB_LOCATION_BASE   0x082c

Definition at line 90 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ mmMMHUB_VM_FB_LOCATION_TOP

#define mmMMHUB_VM_FB_LOCATION_TOP   0x082d

Definition at line 91 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ mmMMHUB_VM_INVALIDATE_ENG17_ACK

#define mmMMHUB_VM_INVALIDATE_ENG17_ACK   0x0706

Definition at line 89 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ mmMMHUB_VM_INVALIDATE_ENG17_REQ

#define mmMMHUB_VM_INVALIDATE_ENG17_REQ   0x06f4

Definition at line 88 of file amdgpu_vm.hh.

◆ mmMMHUB_VM_INVALIDATE_ENG17_SEM

#define mmMMHUB_VM_INVALIDATE_ENG17_SEM   0x06e2

Definition at line 87 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32

#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32   0x08ec

Definition at line 56 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32

#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32   0x08eb

Definition at line 55 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32

#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32   0x092c

Definition at line 60 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32

#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32   0x092b

Definition at line 59 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32

#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32   0x090c

Definition at line 58 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32

#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32   0x090b

Definition at line 57 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::writeMMIOGfx900().

◆ mmVM_INVALIDATE_ENG17_ACK

#define mmVM_INVALIDATE_ENG17_ACK   0x08c6

MMIO offsets for graphics register bus manager (GRBM).

These values were taken from linux header files. The header files can be found here:

https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/ asic_reg/gc/gc_9_0_offset.h https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/ asic_reg/mmhub/mmhub_1_0_offset.h

Definition at line 54 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::readMMIO().

◆ VEGA10_FB_LOCATION_BASE

#define VEGA10_FB_LOCATION_BASE   0x6a0b0

Definition at line 93 of file amdgpu_vm.hh.

◆ VEGA10_FB_LOCATION_TOP

#define VEGA10_FB_LOCATION_TOP   0x6a0b4

Definition at line 94 of file amdgpu_vm.hh.

Variable Documentation

◆ AMDGPU_AGP_PAGE_SIZE

int AMDGPU_AGP_PAGE_SIZE = 4096
staticconstexpr

Definition at line 113 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::AGPTranslationGen::translate().

◆ AMDGPU_GART_PAGE_SIZE

int AMDGPU_GART_PAGE_SIZE = 4096
staticconstexpr

Definition at line 114 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::GARTTranslationGen::translate().

◆ AMDGPU_MMHUB_PAGE_SIZE

int AMDGPU_MMHUB_PAGE_SIZE = 4096
staticconstexpr

Definition at line 115 of file amdgpu_vm.hh.

Referenced by gem5::SDMAEngine::constFill(), gem5::SDMAEngine::copy(), gem5::SDMAEngine::copyReadData(), and gem5::AMDGPUVM::MMHUBTranslationGen::translate().

◆ AMDGPU_USER_PAGE_SIZE

int AMDGPU_USER_PAGE_SIZE = 4096
staticconstexpr

Definition at line 118 of file amdgpu_vm.hh.

Referenced by gem5::AMDGPUVM::UserTranslationGen::translate().

◆ AMDGPU_VM_COUNT

int AMDGPU_VM_COUNT = 16
staticconstexpr

Definition at line 110 of file amdgpu_vm.hh.

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