47#include "debug/Decoder.hh"
48#include "params/ArmDecoder.hh"
67 getCurSveVecLenInBitsAtReset() >> 7) - 1;
71 ->getCurSmeVecLenInBitsAtReset() >> 7) - 1;
75 "DVM Ops instructions are micro-architecturally "
76 "modelled as loads. This will tamper the effective "
77 "number of loads stat\n");
110 emi.instBits =
emi.instBits | word;
116 uint16_t highBits = word & 0xF800;
117 if (highBits == 0xE800 || highBits == 0xF000 ||
118 highBits == 0xF800) {
130 "First half of 32 bit Thumb.\n");
131 emi.instBits = (uint32_t)word << 16;
145 if (
bits(word, 15, 8) == 0xbf &&
146 bits(word, 3, 0) != 0x0) {
150 "IT detected, cond = %#x, mask = %#x\n",
172 offset = (fetchPC >=
pc.instAddr()) ? 0 :
pc.instAddr() - fetchPC;
173 emi.thumb =
pc.thumb();
174 emi.aarch64 =
pc.aarch64();
179 const Addr alignment(
pc.thumb() ? 0x1 : 0x3);
180 emi.decoderFault =
static_cast<uint8_t
>(
195 const int inst_size((!
emi.thumb ||
emi.bigThumb) ? 4 : 2);
198 pc.npc(
pc.pc() + inst_size);
201 this_emi.itstate =
pc.itstate();
202 this_emi.illegalExecution =
pc.illegalExec() ? 1 : 0;
203 this_emi.debugStep =
pc.debugStep() ? 1 : 0;
210 return decode(this_emi,
pc.instAddr());
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
enums::DecoderFlavor decoderFlavor
void reset() override
Reset the decoders internal state.
Decoder(const ArmDecoderParams ¶ms)
int smeLen
SME vector length, encoded in the same format as the SMCR_EL<x>.LEN bitfields.
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
void process()
Pre-decode an instruction from the current state of the decoder.
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
const bool dvmEnabled
True if the decoder should emit DVM Ops (treated as Loads)
InstDecoder(const InstDecoderParams ¶ms, MoreBytesType *mb_buf)
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
const Params & params() const
@ UNALIGNED
Unaligned instruction fault.
Copyright (c) 2024 Arm Limited All rights reserved.
T safe_cast(U &&ref_or_ptr)
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
RefCountingPtr< StaticInst > StaticInstPtr