gem5 [DEVELOP-FOR-25.1]
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decoder.cc
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1/*
2 * Copyright (c) 2012-2014,2018, 2021 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2012 Google
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#include "arch/arm/decoder.hh"
42
43#include "arch/arm/isa.hh"
44#include "arch/arm/utility.hh"
45#include "base/cast.hh"
46#include "base/trace.hh"
47#include "debug/Decoder.hh"
48#include "params/ArmDecoder.hh"
49#include "sim/full_system.hh"
50
51namespace gem5
52{
53
54namespace ArmISA
55{
56
57Decoder::Decoder(const ArmDecoderParams &params)
59 dvmEnabled(params.dvm_enabled),
60 data(0), fpscrLen(0), fpscrStride(0),
62{
63 reset();
64
65 // Initialize SVE vector length
67 getCurSveVecLenInBitsAtReset() >> 7) - 1;
68
69 // Initialize SME vector length
71 ->getCurSmeVecLenInBitsAtReset() >> 7) - 1;
72
73 if (dvmEnabled) {
75 "DVM Ops instructions are micro-architecturally "
76 "modelled as loads. This will tamper the effective "
77 "number of loads stat\n");
78 }
79}
80
81void
83{
85 bigThumb = false;
86 offset = 0;
87 emi = 0;
88 foundIt = false;
89}
90
91void
93{
94 // emi is typically ready, with some caveats below...
95 instDone = true;
96
97 if (!emi.thumb) {
98 emi.instBits = data;
99 if (!emi.aarch64) {
100 emi.sevenAndFour = bits(data, 7) && bits(data, 4);
101 emi.isMisc = (bits(data, 24, 23) == 0x2 &&
102 bits(data, 20) == 0);
103 }
104 consumeBytes(4);
105 DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
106 } else {
107 uint16_t word = (data >> (offset * 8));
108 if (bigThumb) {
109 // A 32 bit thumb inst is half collected.
110 emi.instBits = emi.instBits | word;
111 bigThumb = false;
112 consumeBytes(2);
113 DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n",
114 emi.instBits);
115 } else {
116 uint16_t highBits = word & 0xF800;
117 if (highBits == 0xE800 || highBits == 0xF000 ||
118 highBits == 0xF800) {
119 // The start of a 32 bit thumb inst.
120 emi.bigThumb = 1;
121 if (offset == 0) {
122 // We've got the whole thing.
123 emi.instBits = (data >> 16) | (data << 16);
124 DPRINTF(Decoder, "All of 32 bit Thumb: %#x.\n",
125 emi.instBits);
126 consumeBytes(4);
127 } else {
128 // We only have the first half word.
130 "First half of 32 bit Thumb.\n");
131 emi.instBits = (uint32_t)word << 16;
132 bigThumb = true;
133 consumeBytes(2);
134 // emi not ready yet.
135 instDone = false;
136 }
137 } else {
138 // A 16 bit thumb inst.
139 consumeBytes(2);
140 emi.instBits = word;
141 // Set the condition code field artificially.
142 emi.condCode = COND_UC;
143 DPRINTF(Decoder, "16 bit Thumb: %#x.\n",
144 emi.instBits);
145 if (bits(word, 15, 8) == 0xbf &&
146 bits(word, 3, 0) != 0x0) {
147 foundIt = true;
148 itBits = bits(word, 7, 0);
150 "IT detected, cond = %#x, mask = %#x\n",
151 itBits.cond, itBits.mask);
152 }
153 }
154 }
155 }
156}
157
158void
160{
161 offset += numBytes;
162 assert(offset <= sizeof(data) || emi.decoderFault);
163 if (offset == sizeof(data))
164 outOfBytes = true;
165}
166
167void
169{
170 auto &pc = _pc.as<PCState>();
171 data = letoh(data);
172 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
173 emi.thumb = pc.thumb();
174 emi.aarch64 = pc.aarch64();
175 emi.fpscrLen = fpscrLen;
176 emi.fpscrStride = fpscrStride;
177 emi.sveLen = sveLen;
178
179 const Addr alignment(pc.thumb() ? 0x1 : 0x3);
180 emi.decoderFault = static_cast<uint8_t>(
181 pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
182
183 outOfBytes = false;
184 process();
185}
186
189{
190 if (!instDone)
191 return NULL;
192
193 auto &pc = _pc.as<PCState>();
194
195 const int inst_size((!emi.thumb || emi.bigThumb) ? 4 : 2);
196 ExtMachInst this_emi(emi);
197
198 pc.npc(pc.pc() + inst_size);
199 if (foundIt)
200 pc.nextItstate(itBits);
201 this_emi.itstate = pc.itstate();
202 this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
203 this_emi.debugStep = pc.debugStep() ? 1 : 0;
204 pc.size(inst_size);
205
206 emi = 0;
207 instDone = false;
208 foundIt = false;
209
210 return decode(this_emi, pc.instAddr());
211}
212
213} // namespace ArmISA
214} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition decoder.cc:159
enums::DecoderFlavor decoderFlavor
Definition decoder.hh:95
void reset() override
Reset the decoders internal state.
Definition decoder.cc:82
Decoder(const ArmDecoderParams &params)
Definition decoder.cc:57
int smeLen
SME vector length, encoded in the same format as the SMCR_EL<x>.LEN bitfields.
Definition decoder.hh:93
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition decoder.hh:137
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition decoder.hh:87
ExtMachInst emi
Definition decoder.hh:73
void process()
Pre-decode an instruction from the current state of the decoder.
Definition decoder.cc:92
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition decoder.cc:168
const bool dvmEnabled
True if the decoder should emit DVM Ops (treated as Loads)
Definition decoder.hh:69
InstDecoder(const InstDecoderParams &params, MoreBytesType *mb_buf)
Definition decoder.hh:54
virtual void reset()
Definition decoder.hh:63
Target & as()
Definition pcstate.hh:73
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
const Params & params() const
#define warn_once(...)
Definition logging.hh:292
@ UNALIGNED
Unaligned instruction fault.
Definition types.hh:398
@ OK
No fault.
Definition types.hh:397
@ COND_UC
Definition cc.hh:120
Bitfield< 4 > pc
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
T letoh(T value)
Definition byteswap.hh:173
T safe_cast(U &&ref_or_ptr)
Definition cast.hh:74
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
RefCountingPtr< StaticInst > StaticInstPtr

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