gem5
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systemc
tests
systemc
misc
synth
bubble
bubble.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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bubble.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/******************************************************************************/
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/*************************** bubble Class Definition ********************/
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/******************************************************************************/
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#include "
common.h
"
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SC_MODULE
( BUBBLE )
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{
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SC_HAS_PROCESS
( BUBBLE );
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sc_in_clk
clk;
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const
sc_signal<bool>
& reset;
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const
sc_signal<bool>
& in_ok;
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const
sc_signal<bool>
& out_ok;
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sc_signal<bool>
& instrb;
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sc_signal<bool>
& outstrb;
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const
signal_bool_vector
&a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;
// -128 to 127
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signal_bool_vector
&d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8;
// -128 to 127
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BUBBLE(
sc_module_name
NAME,
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sc_clock
& TICK_P,
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const
sc_signal<bool>
& RESET,
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const
sc_signal<bool>
& IN_OK,
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const
sc_signal<bool>
& OUT_OK,
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sc_signal<bool>
& INSTRB,
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sc_signal<bool>
& OUTSTRB,
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const
signal_bool_vector
& A1,
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const
signal_bool_vector
& A2,
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const
signal_bool_vector
& A3,
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const
signal_bool_vector
& A4,
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const
signal_bool_vector
& A5,
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const
signal_bool_vector
& A6,
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const
signal_bool_vector
& A7,
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const
signal_bool_vector
& A8,
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signal_bool_vector
& D1,
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signal_bool_vector
& D2,
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signal_bool_vector
& D3,
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signal_bool_vector
& D4,
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signal_bool_vector
& D5,
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signal_bool_vector
& D6,
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signal_bool_vector
& D7,
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signal_bool_vector
& D8
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)
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:
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reset (RESET),
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in_ok (IN_OK),
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out_ok (OUT_OK),
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instrb (INSTRB),
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outstrb (OUTSTRB),
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a1 (A1), a2(A2), a3(A3), a4(A4),
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a5 (A5), a6(A6), a7(A7), a8(A8),
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d1 (D1), d2(D2), d3(D3), d4(D4),
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d5 (D5), d6(D6), d7(D7), d8(D8)
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{
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clk(TICK_P);
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SC_CTHREAD
( entry, clk.pos() );
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reset_signal_is(reset,
true
);
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}
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void
entry();
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};
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/******************************************************************************/
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/*************************** bubble Entry Function **********************/
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/******************************************************************************/
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/******************************************************************************/
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void
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BUBBLE::entry()
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{
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bool_vector
B[9];
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bool_vector
C
[9];
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int
minel;
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int
x
;
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int
i
;
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int
j;
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// RESET INITIALIZATION
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while
(
true
) {
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instrb.write(
false
);
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outstrb.write(
false
);
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minel = -500;
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x
= 0;
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d1
.write(0);
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d2
.write(0);
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d3.write(0);
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d4.write(0);
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d5.write(0);
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d6.write(0);
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d7.write(0);
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d8.write(0);
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for
(i = 1;
i
<= 8;
i
++) {
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B[
i
] = 0;
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}
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for
(i = 1;
i
<= 8;
i
++) {
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C
[
i
] = 0;
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}
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wait
();
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// READY SIGNAL FOR INPUT DATA
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wait
();
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instrb.write(
true
);
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wait
();
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// INPUT HANDSHAKE & INPUT READ
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do
{
wait
(); }
while
(!in_ok);
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instrb.write(
false
);
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wait
();
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B[1] =
a1
.read(); B[2] = a2.read(); B[3] = a3.read(); B[4] = a4.read();
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B[5] = a5.read(); B[6] = a6.read(); B[7] = a7.read(); B[8] = a8.read();
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wait
();
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lout
<<
"STARTING BUBBLE SORT"
<< endl;
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// BUBBLE SORT ALGORITHM
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// EVERY ELEMENT
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for
(i = 1;
i
<= 7;
i
++) {
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if
(B[i].to_int() > B[i+1].to_int()) {
// if #1
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for
(j = 1; j <= 8; j++) {
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C
[j] = B[j];
// COPY
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}
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B[
i
] = B[
i
+1];
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B[
i
+1] =
C
[
i
];
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minel =
C
[
i
].to_int();
// MOVE
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for
(j = 1; j <= 8; j++) {
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C
[j] = B[j];
// COPY
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}
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if
(i >= 2) {
// if #2
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x
=
i
;
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while
(x > 1) {
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if
(B[x].to_int() > B[x-1].to_int()) {
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break
;
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}
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else
{
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for
(j = 1; j <= 8; j++) {
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C
[j] = B[j];
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}
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B[
x
] = B[
x
-1];
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B[
x
-1] =
C
[
x
];
// MOVE
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for
(j = 1; j <= 8; j++) {
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C
[j] = B[j];
// COPY
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}
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}
// end else
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x
=
x
-1;
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}
// end WHL Loop
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}
// end if #2
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}
// end if #1;
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}
// end FL3 Loop
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wait
();
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// WRITE OUTPUT & OUTPUT HANDSHAKE
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d1
.write(C[1]);
d2
.write(C[2]); d3.write(C[3]); d4.write(C[4]);
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d5.write(C[5]); d6.write(C[6]); d7.write(C[7]); d8.write(C[8]);
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outstrb.write(
true
);
// Ready to give output data
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wait
();
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do
{
wait
(); }
while
(!out_ok);
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outstrb.write(
false
);
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wait
();
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}
// end Reset Loop
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}
sc_in_clk
sc_in< bool > sc_in_clk
Definition
sc_clock.hh:116
sc_clock
Definition
sc_clock.hh:50
sc_module_name
Definition
sc_module_name.hh:42
sc_signal
Definition
sc_signal.hh:273
wait
void wait()
Definition
sc_module.cc:653
gem5::ArmISA::cc_reg::C
constexpr RegId C
Definition
cc.hh:95
gem5::ArmISA::a1
Bitfield< 22 > a1
Definition
misc_types.hh:587
gem5::ArmISA::i
Bitfield< 7 > i
Definition
misc_types.hh:67
gem5::PowerISA::d1
Bitfield< 20, 16 > d1
Definition
types.hh:66
gem5::PowerISA::d2
Bitfield< 1, 0 > d2
Definition
types.hh:67
gem5::VegaISA::x
Bitfield< 4 > x
Definition
pagetable.hh:61
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition
sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition
sc_module.hh:295
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition
sc_module.hh:301
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition
common.h:44
bool_vector
sc_bv< 16 > bool_vector
Definition
common.h:43
common.h
lout
ofstream lout("systemc.log")
Display to standard out and to logfile "systemc.log".
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