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systemc
tests
systemc
misc
user_guide
chpt12.2
accessor.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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accessor.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/* Filename accessor.h */
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/* This is the interface file for synchronous process 'accessor' */
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#include "
common.h
"
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SC_MODULE
( accessor )
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{
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SC_HAS_PROCESS
( accessor );
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sc_in_clk
clk;
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const
signal_bool_vector32
& datain;
//input
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sc_signal<bool>
& chip_select;
//output
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sc_signal<bool>
& write_enable;
//output
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signal_bool_vector10
& address;
//output
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signal_bool_vector32
& dataout;
//output
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// Parameter
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const
int
memory_latency;
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//Constructor
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accessor(
sc_module_name
NAME,
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sc_clock
& CLK,
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const
signal_bool_vector32
& DATAIN,
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sc_signal<bool>
& CHIP_SELECT,
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sc_signal<bool>
& WRITE_ENABLE,
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signal_bool_vector10
& ADDRESS,
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signal_bool_vector32
& DATAOUT,
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const
int
MEMORY_LATENCY = 1)
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: datain(DATAIN), chip_select(CHIP_SELECT),
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write_enable(WRITE_ENABLE), address(ADDRESS), dataout(DATAOUT),
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memory_latency(MEMORY_LATENCY)
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{
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clk(CLK);
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SC_CTHREAD
( entry, clk.pos() );
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}
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// Process functionality in member function below
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void
entry();
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};
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sc_in_clk
sc_in< bool > sc_in_clk
Definition
sc_clock.hh:116
sc_clock
Definition
sc_clock.hh:50
sc_module_name
Definition
sc_module_name.hh:42
sc_signal
Definition
sc_signal.hh:273
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition
sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition
sc_module.hh:295
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition
sc_module.hh:301
signal_bool_vector32
sc_signal< sc_bv< 32 > > signal_bool_vector32
Definition
common.h:44
signal_bool_vector10
sc_signal< sc_bv< 10 > > signal_bool_vector10
Definition
common.h:43
common.h
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