gem5 [DEVELOP-FOR-25.1]
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Public Member Functions | Private Types | Private Attributes | List of all members
gem5::AMDGPUNbio Class Reference

#include <amdgpu_nbio.hh>

Public Member Functions

 AMDGPUNbio ()
void setGPUDevice (AMDGPUDevice *gpu_device)
void readMMIO (PacketPtr pkt, Addr offset)
void writeMMIO (PacketPtr pkt, Addr offset)
bool readFrame (PacketPtr pkt, Addr offset)
void writeFrame (PacketPtr pkt, Addr offset)
bool is_MI200_regBM_PAGE_TABLE_BASE_ADDR (Addr offset)
bool is_MI200_regBM_PAGE_TABLE_START_ADDR (Addr offset)
bool is_MI200_regBM_PAGE_TABLE_END_ADDR (Addr offset)
uint16_t get_context_from_MI200_regBM_PAGE_TABLE_BASE_ADDR (Addr offset)
uint16_t get_context_from_MI200_regBM_PAGE_TABLE_START_ADDR (Addr offset)
uint16_t get_context_from_MI200_regBM_PAGE_TABLE_END_ADDR (Addr offset)

Private Types

using GPURegMap = std::unordered_map<uint64_t, uint32_t>

Private Attributes

AMDGPUDevice * gpuDevice
uint64_t mm_index_reg = 0
uint32_t pcie_index_reg = 0
uint32_t pcie_index2_reg = 0
std::unordered_map< uint32_t, uint32_t > triggered_reads
Addr psp_ring = 0
Addr psp_ring_dev_addr = 0
Addr psp_ring_listen_addr = 0
int psp_ring_size = 0
int psp_ring_value = 0
GPURegMap regs

Detailed Description

Definition at line 121 of file amdgpu_nbio.hh.

Member Typedef Documentation

◆ GPURegMap

using gem5::AMDGPUNbio::GPURegMap = std::unordered_map<uint64_t, uint32_t>
private

Definition at line 192 of file amdgpu_nbio.hh.

Constructor & Destructor Documentation

◆ AMDGPUNbio()

gem5::AMDGPUNbio::AMDGPUNbio ( )

Definition at line 41 of file amdgpu_nbio.cc.

References AMDGPU_MP0_SMN_C2PMSG_64, and triggered_reads.

Member Function Documentation

◆ get_context_from_MI200_regBM_PAGE_TABLE_BASE_ADDR()

uint16_t gem5::AMDGPUNbio::get_context_from_MI200_regBM_PAGE_TABLE_BASE_ADDR ( Addr offset)
inline

Definition at line 157 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_BASE_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ get_context_from_MI200_regBM_PAGE_TABLE_END_ADDR()

uint16_t gem5::AMDGPUNbio::get_context_from_MI200_regBM_PAGE_TABLE_END_ADDR ( Addr offset)
inline

Definition at line 165 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_END_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ get_context_from_MI200_regBM_PAGE_TABLE_START_ADDR()

uint16_t gem5::AMDGPUNbio::get_context_from_MI200_regBM_PAGE_TABLE_START_ADDR ( Addr offset)
inline

Definition at line 161 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_START_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ is_MI200_regBM_PAGE_TABLE_BASE_ADDR()

bool gem5::AMDGPUNbio::is_MI200_regBM_PAGE_TABLE_BASE_ADDR ( Addr offset)
inline

Definition at line 134 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_BASE_ADDR_END, MI200_REG_BM_PAGE_TABLE_BASE_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ is_MI200_regBM_PAGE_TABLE_END_ADDR()

bool gem5::AMDGPUNbio::is_MI200_regBM_PAGE_TABLE_END_ADDR ( Addr offset)
inline

Definition at line 146 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_END_ADDR_END, MI200_REG_BM_PAGE_TABLE_END_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ is_MI200_regBM_PAGE_TABLE_START_ADDR()

bool gem5::AMDGPUNbio::is_MI200_regBM_PAGE_TABLE_START_ADDR ( Addr offset)
inline

Definition at line 140 of file amdgpu_nbio.hh.

References MI200_REG_BM_PAGE_TABLE_START_ADDR_END, MI200_REG_BM_PAGE_TABLE_START_ADDR_START, and gem5::ArmISA::offset.

Referenced by writeMMIO().

◆ readFrame()

bool gem5::AMDGPUNbio::readFrame ( PacketPtr pkt,
Addr offset )

Definition at line 263 of file amdgpu_nbio.cc.

References gem5::ArmISA::offset, psp_ring_dev_addr, psp_ring_value, and gem5::Packet::setUintX().

◆ readMMIO()

void gem5::AMDGPUNbio::readMMIO ( PacketPtr pkt,
Addr offset )

Definition at line 54 of file amdgpu_nbio.cc.

References AMDGPU_MM_DATA, AMDGPU_MP0_SMN_C2PMSG_35, AMDGPU_MP1_SMN_C2PMSG_90, AMDGPU_PCIE_DATA, AMDGPU_PCIE_DATA2, AMDGPU_PCIE_INDEX, AMDGPU_PCIE_INDEX2, DPRINTF, gem5::Packet::getAddr(), gpuDevice, MI100_INV_ENG17_ACK2, MI100_INV_ENG17_ACK3, MI100_INV_ENG17_SEM2, MI100_INV_ENG17_SEM3, MI200_BIOS_SCRATCH_7, MI200_INV_ENG17_ACK2, MI200_INV_ENG17_SEM2, MI300X_EPF0_STRAP0, MI300X_INV_ENG17_ACK1, MI300X_INV_ENG17_ACK10, MI300X_INV_ENG17_ACK11, MI300X_INV_ENG17_ACK2, MI300X_INV_ENG17_ACK3, MI300X_INV_ENG17_ACK4, MI300X_INV_ENG17_ACK5, MI300X_INV_ENG17_ACK6, MI300X_INV_ENG17_ACK7, MI300X_INV_ENG17_ACK8, MI300X_INV_ENG17_ACK9, mm_index_reg, gem5::ArmISA::offset, pcie_index2_reg, pcie_index_reg, regs, gem5::Packet::setLE(), triggered_reads, VEGA10_INV_ENG17_ACK1, VEGA10_INV_ENG17_ACK2, VEGA10_INV_ENG17_SEM1, and VEGA10_INV_ENG17_SEM2.

◆ setGPUDevice()

void gem5::AMDGPUNbio::setGPUDevice ( AMDGPUDevice * gpu_device)

Definition at line 48 of file amdgpu_nbio.cc.

References gpuDevice.

◆ writeFrame()

void gem5::AMDGPUNbio::writeFrame ( PacketPtr pkt,
Addr offset )

Definition at line 276 of file amdgpu_nbio.cc.

References DPRINTF, gem5::Packet::getLE(), gem5::Packet::getSize(), gem5::Packet::getUintX(), gpuDevice, gem5::ArmISA::offset, panic, psp_ring_dev_addr, and psp_ring_listen_addr.

◆ writeMMIO()

void gem5::AMDGPUNbio::writeMMIO ( PacketPtr pkt,
Addr offset )

Definition at line 157 of file amdgpu_nbio.cc.

References AMDGPU_MM_DATA, AMDGPU_MM_INDEX, AMDGPU_MM_INDEX_HI, AMDGPU_MP0_SMN_C2PMSG_35, AMDGPU_MP0_SMN_C2PMSG_64, AMDGPU_MP0_SMN_C2PMSG_69, AMDGPU_MP0_SMN_C2PMSG_70, AMDGPU_MP0_SMN_C2PMSG_71, AMDGPU_MP0_SMN_C2PMSG_81, AMDGPU_PCIE_DATA, AMDGPU_PCIE_DATA2, AMDGPU_PCIE_INDEX, AMDGPU_PCIE_INDEX2, DPRINTF, get_context_from_MI200_regBM_PAGE_TABLE_BASE_ADDR(), get_context_from_MI200_regBM_PAGE_TABLE_END_ADDR(), get_context_from_MI200_regBM_PAGE_TABLE_START_ADDR(), gem5::Packet::getLE(), gem5::Packet::getSize(), gpuDevice, gem5::insertBits(), is_MI200_regBM_PAGE_TABLE_BASE_ADDR(), is_MI200_regBM_PAGE_TABLE_END_ADDR(), is_MI200_regBM_PAGE_TABLE_START_ADDR(), mm_index_reg, gem5::ArmISA::offset, pcie_index2_reg, pcie_index_reg, psp_ring, psp_ring_listen_addr, psp_ring_size, regs, and triggered_reads.

Member Data Documentation

◆ gpuDevice

AMDGPUDevice* gem5::AMDGPUNbio::gpuDevice
private

Definition at line 170 of file amdgpu_nbio.hh.

Referenced by readMMIO(), setGPUDevice(), writeFrame(), and writeMMIO().

◆ mm_index_reg

uint64_t gem5::AMDGPUNbio::mm_index_reg = 0
private

Definition at line 175 of file amdgpu_nbio.hh.

Referenced by readMMIO(), and writeMMIO().

◆ pcie_index2_reg

uint32_t gem5::AMDGPUNbio::pcie_index2_reg = 0
private

Definition at line 177 of file amdgpu_nbio.hh.

Referenced by readMMIO(), and writeMMIO().

◆ pcie_index_reg

uint32_t gem5::AMDGPUNbio::pcie_index_reg = 0
private

Definition at line 176 of file amdgpu_nbio.hh.

Referenced by readMMIO(), and writeMMIO().

◆ psp_ring

Addr gem5::AMDGPUNbio::psp_ring = 0
private

Definition at line 183 of file amdgpu_nbio.hh.

Referenced by writeMMIO().

◆ psp_ring_dev_addr

Addr gem5::AMDGPUNbio::psp_ring_dev_addr = 0
private

Definition at line 184 of file amdgpu_nbio.hh.

Referenced by readFrame(), and writeFrame().

◆ psp_ring_listen_addr

Addr gem5::AMDGPUNbio::psp_ring_listen_addr = 0
private

Definition at line 185 of file amdgpu_nbio.hh.

Referenced by writeFrame(), and writeMMIO().

◆ psp_ring_size

int gem5::AMDGPUNbio::psp_ring_size = 0
private

Definition at line 186 of file amdgpu_nbio.hh.

Referenced by writeMMIO().

◆ psp_ring_value

int gem5::AMDGPUNbio::psp_ring_value = 0
private

Definition at line 187 of file amdgpu_nbio.hh.

Referenced by readFrame().

◆ regs

GPURegMap gem5::AMDGPUNbio::regs
private

Definition at line 193 of file amdgpu_nbio.hh.

Referenced by readMMIO(), and writeMMIO().

◆ triggered_reads

std::unordered_map<uint32_t, uint32_t> gem5::AMDGPUNbio::triggered_reads
private

Definition at line 178 of file amdgpu_nbio.hh.

Referenced by AMDGPUNbio(), readMMIO(), and writeMMIO().

The documentation for this class was generated from the following files:
Generated on Mon Oct 27 2025 04:13:08 for gem5 by doxygen 1.14.0