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gem5 [DEVELOP-FOR-25.0]
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This is the complete list of members for gem5::ArmISA::DTLBIMVA, including all inherited members.
| addr | gem5::ArmISA::TLBIMVA | |
| asid | gem5::ArmISA::TLBIMVA | |
| Attr enum name | gem5::ArmISA::TLBIOp | |
| attr | gem5::ArmISA::TLBIOp | |
| broadcast(ThreadContext *tc) | gem5::ArmISA::TLBIOp | inline |
| DTLBIMVA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, uint16_t _asid) | gem5::ArmISA::DTLBIMVA | inline |
| lastLevel | gem5::ArmISA::TLBIMVA | |
| lookupGen(vmid_t vmid) const | gem5::ArmISA::TLBIMVA | protected |
| match(TlbEntry *entry, vmid_t curr_vmid) const | gem5::ArmISA::TLBIOp | |
| matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override | gem5::ArmISA::DTLBIMVA | virtual |
| operator()(ThreadContext *tc) override | gem5::ArmISA::DTLBIMVA | virtual |
| ss | gem5::ArmISA::TLBIOp | |
| stage1Flush() const | gem5::ArmISA::TLBIOp | inlinevirtual |
| stage2Flush() const | gem5::ArmISA::TLBIOp | inlinevirtual |
| targetRegime | gem5::ArmISA::TLBIOp | |
| TLBIMVA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, uint16_t _asid, bool last_level, Attr _attr=Attr::None) | gem5::ArmISA::TLBIMVA | inline |
| TLBIOp(TranslationRegime _target_regime, SecurityState _ss, Attr _attr) | gem5::ArmISA::TLBIOp | inline |
| ~TLBIOp() | gem5::ArmISA::TLBIOp | inlinevirtual |