gem5::ArmISA::TLBIOp Class Reference

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIOp:

Public Types
enum class	Attr { None , ExcludeXS }

Public Member Functions
	TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr)
virtual	~TLBIOp ()
virtual void	operator() (ThreadContext *tc)
void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
bool	match (TlbEntry *entry, vmid_t curr_vmid) const
virtual bool	matchEntry (TlbEntry *entry, vmid_t curr_vmid) const =0
virtual bool	stage1Flush () const
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.
virtual bool	stage2Flush () const
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Public Attributes
SecurityState	ss
TranslationRegime	targetRegime
Attr	attr

Detailed Description

Definition at line 57 of file tlbi_op.hh.

Member Enumeration Documentation

Attr

enum class gem5::ArmISA::TLBIOp::Attr

strong

Enumerator
None
ExcludeXS

Definition at line 60 of file tlbi_op.hh.

Constructor & Destructor Documentation

TLBIOp()

gem5::ArmISA::TLBIOp::TLBIOp ( TranslationRegime _target_regime, SecurityState _ss, Attr _attr )

inline

Definition at line 66 of file tlbi_op.hh.

References attr, ss, and targetRegime.

Referenced by gem5::ArmISA::TLBIALL::TLBIALL(), gem5::ArmISA::TLBIALLEL::TLBIALLEL(), gem5::ArmISA::TLBIALLN::TLBIALLN(), gem5::ArmISA::TLBIASID::TLBIASID(), gem5::ArmISA::TLBIIPA::TLBIIPA(), gem5::ArmISA::TLBIIPA::TLBIIPA(), gem5::ArmISA::TLBIMVA::TLBIMVA(), gem5::ArmISA::TLBIMVAA::TLBIMVAA(), and gem5::ArmISA::TLBIVMALL::TLBIVMALL().

~TLBIOp()

virtual gem5::ArmISA::TLBIOp::~TLBIOp ( )

inlinevirtual

Definition at line 70 of file tlbi_op.hh.

Member Function Documentation

broadcast()

void gem5::ArmISA::TLBIOp::broadcast ( ThreadContext * tc )

inline

Broadcast the TLB Invalidate operation to all TLBs in the Arm system.

Parameters

tc	Thread Context

Definition at line 79 of file tlbi_op.hh.

References gem5::ThreadContext::getSystemPtr(), and gem5::System::threads.

Referenced by gem5::TlbiOp::performTlbi(), gem5::TlbiOp64::tlbiAll(), gem5::TlbiOp64::tlbiAsid(), gem5::TlbiOp64::tlbiIpaS2(), gem5::TlbiOp64::tlbiRipaS2(), gem5::TlbiOp64::tlbiRva(), gem5::TlbiOp64::tlbiRvaa(), gem5::TlbiOp64::tlbiVa(), gem5::TlbiOp64::tlbiVaa(), and gem5::TlbiOp64::tlbiVmall().

match()

bool gem5::ArmISA::TLBIOp::match	(	TlbEntry *	entry,
		vmid_t	curr_vmid ) const

Definition at line 49 of file tlbi_op.cc.

References attr, ExcludeXS, matchEntry(), and gem5::ArmISA::te.

Referenced by gem5::ArmISA::TLB::flush().

matchEntry()

virtual bool gem5::ArmISA::TLBIOp::matchEntry ( TlbEntry * entry, vmid_t curr_vmid ) const

pure virtual

Implemented in gem5::ArmISA::DTLBIALL, gem5::ArmISA::DTLBIASID, gem5::ArmISA::DTLBIMVA, gem5::ArmISA::ITLBIALL, gem5::ArmISA::ITLBIASID, gem5::ArmISA::ITLBIMVA, gem5::ArmISA::TLBIALL, gem5::ArmISA::TLBIALLEL, gem5::ArmISA::TLBIALLN, gem5::ArmISA::TLBIASID, gem5::ArmISA::TLBIIPA, gem5::ArmISA::TLBIMVA, gem5::ArmISA::TLBIMVAA, gem5::ArmISA::TLBIRIPA, gem5::ArmISA::TLBIRMVA, gem5::ArmISA::TLBIRMVAA, and gem5::ArmISA::TLBIVMALL.

Referenced by match().

operator()()

virtual void gem5::ArmISA::TLBIOp::operator() ( ThreadContext * tc )

inlinevirtual

Reimplemented in gem5::ArmISA::DTLBIALL, gem5::ArmISA::DTLBIASID, gem5::ArmISA::DTLBIMVA, gem5::ArmISA::ITLBIALL, gem5::ArmISA::ITLBIASID, gem5::ArmISA::ITLBIMVA, gem5::ArmISA::TLBIALL, gem5::ArmISA::TLBIALLEL, gem5::ArmISA::TLBIALLN, gem5::ArmISA::TLBIASID, gem5::ArmISA::TLBIIPA, gem5::ArmISA::TLBIMVA, gem5::ArmISA::TLBIMVAA, and gem5::ArmISA::TLBIVMALL.

Definition at line 71 of file tlbi_op.hh.

stage1Flush()

virtual bool gem5::ArmISA::TLBIOp::stage1Flush ( ) const

inlinevirtual

Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Reimplemented in gem5::ArmISA::TLBIIPA.

Definition at line 95 of file tlbi_op.hh.

Referenced by gem5::ArmISA::MMU::flush().

stage2Flush()

virtual bool gem5::ArmISA::TLBIOp::stage2Flush ( ) const

inlinevirtual

Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Reimplemented in gem5::ArmISA::TLBIALL, gem5::ArmISA::TLBIALLEL, gem5::ArmISA::TLBIALLN, and gem5::ArmISA::TLBIVMALL.

Definition at line 106 of file tlbi_op.hh.

Referenced by gem5::ArmISA::MMU::flush().

Member Data Documentation

attr

Attr gem5::ArmISA::TLBIOp::attr

Definition at line 113 of file tlbi_op.hh.

Referenced by match(), and TLBIOp().

ss

SecurityState gem5::ArmISA::TLBIOp::ss

Definition at line 111 of file tlbi_op.hh.

Referenced by gem5::ArmISA::TLBIIPA::lookupGen(), gem5::ArmISA::TLBIMVA::lookupGen(), gem5::ArmISA::TLBIMVAA::lookupGen(), gem5::ArmISA::TLBIALL::matchEntry(), gem5::ArmISA::TLBIALLEL::matchEntry(), gem5::ArmISA::TLBIASID::matchEntry(), gem5::ArmISA::TLBIVMALL::matchEntry(), gem5::ArmISA::TLBIIPA::TLBIIPA(), and TLBIOp().

targetRegime

TranslationRegime gem5::ArmISA::TLBIOp::targetRegime

Definition at line 112 of file tlbi_op.hh.

Referenced by gem5::ArmISA::TLBIIPA::lookupGen(), gem5::ArmISA::TLBIMVA::lookupGen(), gem5::ArmISA::TLBIMVAA::lookupGen(), gem5::ArmISA::TLBIALL::matchEntry(), gem5::ArmISA::TLBIALLEL::matchEntry(), gem5::ArmISA::TLBIALLN::matchEntry(), gem5::ArmISA::TLBIASID::matchEntry(), gem5::ArmISA::TLBIVMALL::matchEntry(), gem5::ArmISA::TLBIALLEL::stage2Flush(), gem5::ArmISA::TLBIALLN::stage2Flush(), and TLBIOp().

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The documentation for this class was generated from the following files:

• arch/arm/tlbi_op.hh
• arch/arm/tlbi_op.cc