#include <faults.hh>
Public Member Functions | |
| void | invoke (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override |
 Public Member Functions inherited from gem5::ArmISA::ArmFaultVals< Reset > | |
| ArmFaultVals (ExtMachInst mach_inst=0, uint32_t _iss=0) | |
| FaultName | name () const override |
| FaultOffset | offset (ThreadContext *tc) override |
| FaultOffset | offset64 (ThreadContext *tc) override |
| OperatingMode | nextMode () override |
| virtual bool | routeToMonitor (ThreadContext *tc) const override |
| uint8_t | armPcOffset (bool is_hyp) override |
| uint8_t | thumbPcOffset (bool is_hyp) override |
| uint8_t | armPcElrOffset () override |
| uint8_t | thumbPcElrOffset () override |
| bool | abortDisable (ThreadContext *tc) override |
| bool | fiqDisable (ThreadContext *tc) override |
| ExceptionClass | ec (ThreadContext *tc) const override |
| Syndrome methods. | |
| bool | il (ThreadContext *tc) const override |
| uint32_t | iss () const override |
| Public Member Functions inherited from gem5::ArmISA::ArmFault | |
| ArmFault (ExtMachInst mach_inst=0, uint32_t _iss=0) | |
| MiscRegIndex | getSyndromeReg64 () const |
| void | invoke32 (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) |
| void | invoke64 (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) |
| virtual void | update (ThreadContext *tc) |
| bool | isResetSPSR () |
| bool | vectorCatch (ThreadContext *tc, const StaticInstPtr &inst) |
| ArmStaticInst * | instrAnnotate (const StaticInstPtr &inst) |
| virtual void | annotate (AnnotationIDs id, uint64_t val) |
| virtual bool | routeToHyp (ThreadContext *tc) const |
| virtual uint32_t | vectorCatchFlag () const |
| virtual bool | isStage2 () const |
| virtual FSR | getFsr (ThreadContext *tc) const |
| virtual void | setSyndrome (ThreadContext *tc, MiscRegIndex syndrome_reg) |
| virtual bool | getFaultVAddr (Addr &va) const |
| OperatingMode | getToMode () const |
| virtual bool | isExternalAbort () const |
| Public Member Functions inherited from gem5::FaultBase | |
| virtual | ~FaultBase () |
Additional Inherited Members | |
| Public Types inherited from gem5::ArmISA::ArmFault | |
| enum | FaultSource { AlignmentFault = 0 , InstructionCacheMaintenance , SynchExtAbtOnTranslTableWalkLL , SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4 , TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4 , AccessFlagLL = TranslationLL + 4 , DomainLL = AccessFlagLL + 4 , PermissionLL = DomainLL + 4 , DebugEvent = PermissionLL + 4 , SynchronousExternalAbort , TLBConflictAbort , SynchPtyErrOnMemoryAccess , AsynchronousExternalAbort , AsynchPtyErrOnMemoryAccess , AddressSizeLL , PrefetchTLBMiss = AddressSizeLL + 4 , PrefetchUncacheable , NumFaultSources , FaultSourceInvalid = 0xff } |
| Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actual encodings based on the current register width state and the translation table format in use. More... | |
| enum | AnnotationIDs { S1PTW , OVA , SAS , SSE , SRT , CM , OFA , WnR , SF , AR } |
| enum | DebugType { NODEBUG = 0 , BRKPOINT , VECTORCATCH , WPOINT_CM , WPOINT_NOCM } |
| Static Public Attributes inherited from gem5::ArmISA::ArmFault | |
| static uint8_t | shortDescFaultSources [NumFaultSources] |
| Encodings of the fault sources when the short-desc. | |
| static uint8_t | longDescFaultSources [NumFaultSources] |
| Encodings of the fault sources when the long-desc. | |
| static uint8_t | aarch64FaultSources [NumFaultSources] |
| Encodings of the fault sources in AArch64 state. | |
| Protected Attributes inherited from gem5::ArmISA::ArmFault | |
| ExtMachInst | machInst |
| uint32_t | issRaw |
| bool | bStep |
| bool | from64 |
| bool | to64 |
| ExceptionLevel | fromEL |
| ExceptionLevel | toEL |
| OperatingMode | fromMode |
| OperatingMode | toMode |
| bool | faultUpdated |
| bool | hypRouted |
| bool | span |
| Static Protected Attributes inherited from gem5::ArmISA::ArmFaultVals< Reset > | |
| static FaultVals | vals |
Detailed Description
Member Function Documentation
◆ getVector()
|
overrideprotectedvirtual |
Reimplemented from gem5::ArmISA::ArmFault.
Definition at line 724 of file faults.cc.
References gem5::RiscvISA::base, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmSystem::haveEL(), gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_MVBAR, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_MON, gem5::ArmISA::offset, gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::readMiscRegNoEffect().
◆ invoke()
|
overridevirtual |
Reimplemented from gem5::ArmISA::ArmFault.
Definition at line 742 of file faults.cc.
References gem5::ThreadContext::clearArchRegs(), gem5::BaseCPU::clearInterrupts(), gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::FullSystem, gem5::ThreadContext::getCpuPtr(), gem5::ArmISA::getMPIDR(), gem5::ThreadContext::getSystemPtr(), gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestELIs64(), gem5::ArmISA::ArmFault::invoke(), gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_VMPIDR, gem5::ArmISA::MODE_HYP, gem5::MipsISA::pc, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscReg(), gem5::ArmSystem::resetAddr(), gem5::ThreadContext::setMiscReg(), and gem5::ThreadContext::threadId().
Referenced by gem5::Gicv3CPUInterface::assertWakeRequest(), gem5::ArmISA::FsWorkload::initState(), and gem5::FVPBasePwrCtrl::startCoreUp().
The documentation for this class was generated from the following files:
Generated on Mon May 26 2025 09:19:29 for gem5 by doxygen 1.13.2