gem5 [DEVELOP-FOR-25.0]
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Public Member Functions | Static Public Member Functions | Protected Member Functions | Private Attributes | List of all members
gem5::ArmISA::SelfDebug Class Reference

#include <self_debug.hh>

Public Member Functions

 SelfDebug ()
 
 ~SelfDebug ()
 
Fault testDebug (ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode)
 
bool enabled () const
 
BrkPoint * getBrkPoint (uint8_t index)
 
bool isDebugEnabledForEL64 (ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
 
bool isDebugEnabledForEL32 (ThreadContext *tc, ExceptionLevel el, bool secure, bool mask)
 
void activateDebug ()
 
bool isDebugEnabled (ThreadContext *tc)
 
void setbSDD (RegVal val)
 
void setMDSCRvals (RegVal val)
 
void setMDBGen (RegVal val)
 
void setenableTDETGE (HCR hcr, HDCR mdcr)
 
void updateOSLock (RegVal val)
 
void updateDBGBCR (int index, DBGBCR val)
 
void updateDBGWCR (int index, DBGWCR val)
 
void setDebugMask (bool mask)
 
bool isAArch32 () const
 
void setAArch32 (ThreadContext *tc)
 
SoftwareStep * getSstep ()
 
bool targetAArch32 (ThreadContext *tc)
 
void init (ThreadContext *tc)
 

Static Public Member Functions

static bool securityStateMatch (ThreadContext *tc, uint8_t ssc, bool hmc)
 

Protected Member Functions

Fault testBreakPoints (ThreadContext *tc, Addr vaddr)
 
Fault testWatchPoints (ThreadContext *tc, Addr vaddr, bool write, bool atomic, unsigned size, bool cm)
 
Fault triggerException (ThreadContext *tc, Addr vaddr)
 
Fault triggerWatchpointException (ThreadContext *tc, Addr vaddr, bool write, bool cm)
 

Private Attributes

std::vector< BrkPoint > arBrkPoints
 
std::vector< WatchPoint > arWatchPoints
 
SoftwareStep * softStep
 
bool enableTdeTge
 
bool mde
 
bool sdd
 
bool kde
 
bool oslk
 
bool aarch32
 
bool to32
 

Detailed Description

Definition at line 241 of file self_debug.hh.

Constructor & Destructor Documentation

◆ SelfDebug()

gem5::ArmISA::SelfDebug::SelfDebug ( )
inline

Definition at line 259 of file self_debug.hh.

References enableTdeTge, kde, mde, oslk, sdd, and softStep.

◆ ~SelfDebug()

gem5::ArmISA::SelfDebug::~SelfDebug ( )
inline

Definition at line 266 of file self_debug.hh.

References softStep.

Member Function Documentation

◆ activateDebug()

void gem5::ArmISA::SelfDebug::activateDebug ( )
inline

Definition at line 314 of file self_debug.hh.

References arBrkPoints, and gem5::MipsISA::p.

◆ enabled()

bool gem5::ArmISA::SelfDebug::enabled ( ) const
inline

Definition at line 283 of file self_debug.hh.

References mde, and softStep.

Referenced by isDebugEnabledForEL32().

◆ getBrkPoint()

BrkPoint * gem5::ArmISA::SelfDebug::getBrkPoint ( uint8_t index)
inline

Definition at line 286 of file self_debug.hh.

References arBrkPoints, and gem5::MipsISA::index.

◆ getSstep()

SoftwareStep * gem5::ArmISA::SelfDebug::getSstep ( )
inline

Definition at line 403 of file self_debug.hh.

References softStep.

◆ init()

void gem5::SelfDebug::init ( ThreadContext * tc)

Definition at line 323 of file self_debug.cc.

References aarch32, arBrkPoints, arWatchPoints, gem5::ArmISA::i, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_DBGBCR0_EL1, gem5::ArmISA::MISCREG_DBGBVR0_EL1, gem5::ArmISA::MISCREG_DBGWCR0_EL1, gem5::ArmISA::MISCREG_DBGWVR0_EL1, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1, gem5::ArmISA::MISCREG_MDCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL3, gem5::ArmISA::MISCREG_MDSCR_EL1, gem5::ArmISA::MISCREG_OSLAR_EL1, gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::readMiscRegNoEffect(), setbSDD(), setenableTDETGE(), setMDSCRvals(), gem5::ArmISA::BrkPoint::updateControl(), gem5::ArmISA::WatchPoint::updateControl(), and updateOSLock().

◆ isAArch32()

bool gem5::ArmISA::SelfDebug::isAArch32 ( ) const
inline

Definition at line 386 of file self_debug.hh.

References aarch32.

◆ isDebugEnabled()

bool gem5::ArmISA::SelfDebug::isDebugEnabled ( ThreadContext * tc)
inline

Definition at line 322 of file self_debug.hh.

References aarch32, gem5::ArmISA::currEL(), gem5::ArmISA::el, isDebugEnabledForEL32(), isDebugEnabledForEL64(), gem5::ArmISA::isSecure(), gem5::ArmISA::MISCREG_CPSR, and gem5::ThreadContext::readMiscReg().

Referenced by testBreakPoints(), and testWatchPoints().

◆ isDebugEnabledForEL32()

bool gem5::SelfDebug::isDebugEnabledForEL32 ( ThreadContext * tc,
ExceptionLevel el,
bool secure,
bool mask )

Definition at line 177 of file self_debug.cc.

References gem5::bits(), gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ELStateUsingAArch32(), enabled(), gem5::ArmSystem::haveEL(), isDebugEnabledForEL64(), gem5::ArmISA::mask, gem5::ArmISA::MISCREG_MDCR_EL3, gem5::ArmISA::MISCREG_SDER, oslk, and gem5::ThreadContext::readMiscReg().

Referenced by isDebugEnabled().

◆ isDebugEnabledForEL64()

bool gem5::SelfDebug::isDebugEnabledForEL64 ( ThreadContext * tc,
ExceptionLevel el,
bool secure,
bool mask )

Definition at line 157 of file self_debug.cc.

References gem5::ArmISA::el, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, enableTdeTge, gem5::ArmSystem::haveEL(), gem5::ArmISA::HaveExt(), kde, gem5::ArmISA::mask, oslk, and sdd.

Referenced by isDebugEnabled(), and isDebugEnabledForEL32().

◆ securityStateMatch()

static bool gem5::ArmISA::SelfDebug::securityStateMatch ( ThreadContext * tc,
uint8_t ssc,
bool hmc )
inlinestatic

Definition at line 292 of file self_debug.hh.

References gem5::ArmISA::b, gem5::ArmISA::hmc, gem5::ArmISA::isSecure(), panic, and gem5::ArmISA::ssc.

Referenced by gem5::ArmISA::BrkPoint::isEnabled(), and gem5::ArmISA::WatchPoint::isEnabled().

◆ setAArch32()

void gem5::ArmISA::SelfDebug::setAArch32 ( ThreadContext * tc)
inline

Definition at line 392 of file self_debug.hh.

References aarch32, gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, and gem5::ArmISA::ELIs32().

Referenced by testBreakPoints(), and testWatchPoints().

◆ setbSDD()

void gem5::ArmISA::SelfDebug::setbSDD ( RegVal val)
inline

Definition at line 336 of file self_debug.hh.

References gem5::bits(), sdd, and gem5::X86ISA::val.

Referenced by init().

◆ setDebugMask()

void gem5::ArmISA::SelfDebug::setDebugMask ( bool mask)
inline

Definition at line 380 of file self_debug.hh.

References gem5::ArmISA::mask, and softStep.

◆ setenableTDETGE()

void gem5::ArmISA::SelfDebug::setenableTDETGE ( HCR hcr,
HDCR mdcr )
inline

Definition at line 356 of file self_debug.hh.

References enableTdeTge.

Referenced by init().

◆ setMDBGen()

void gem5::ArmISA::SelfDebug::setMDBGen ( RegVal val)
inline

Definition at line 350 of file self_debug.hh.

References gem5::bits(), mde, and gem5::X86ISA::val.

◆ setMDSCRvals()

void gem5::ArmISA::SelfDebug::setMDSCRvals ( RegVal val)
inline

Definition at line 342 of file self_debug.hh.

References gem5::bits(), kde, mde, softStep, and gem5::X86ISA::val.

Referenced by init().

◆ targetAArch32()

bool gem5::ArmISA::SelfDebug::targetAArch32 ( ThreadContext * tc)
inline

Definition at line 409 of file self_debug.hh.

References aarch32, gem5::ArmISA::debugTargetFrom(), gem5::ArmISA::ELIs32(), and gem5::ArmISA::isSecure().

Referenced by testBreakPoints(), and testWatchPoints().

◆ testBreakPoints()

Fault gem5::SelfDebug::testBreakPoints ( ThreadContext * tc,
Addr vaddr )
protected

Definition at line 74 of file self_debug.cc.

References arBrkPoints, gem5::PCStateBase::as(), gem5::ArmISA::currEL(), gem5::ArmISA::el, isDebugEnabled(), mde, gem5::NoFault, gem5::MipsISA::p, gem5::GenericISA::PCStateWithNext::pc(), gem5::MipsISA::pc, gem5::ThreadContext::pcState(), setAArch32(), targetAArch32(), to32, triggerException(), and gem5::MipsISA::vaddr.

Referenced by testDebug().

◆ testDebug()

Fault gem5::SelfDebug::testDebug ( ThreadContext * tc,
const RequestPtr & req,
BaseMMU::Mode mode )

Definition at line 51 of file self_debug.cc.

References gem5::BaseMMU::Execute, gem5::ArmISA::md, gem5::ArmISA::mode, gem5::NoFault, softStep, testBreakPoints(), testWatchPoints(), and gem5::BaseMMU::Write.

◆ testWatchPoints()

Fault gem5::SelfDebug::testWatchPoints ( ThreadContext * tc,
Addr vaddr,
bool write,
bool atomic,
unsigned size,
bool cm )
protected

Definition at line 121 of file self_debug.cc.

References arWatchPoints, gem5::ArmISA::atomic, gem5::ArmISA::cm, gem5::ArmISA::currEL(), gem5::ArmISA::el, isDebugEnabled(), mde, gem5::NoFault, gem5::MipsISA::p, setAArch32(), targetAArch32(), to32, triggerWatchpointException(), and gem5::MipsISA::vaddr.

Referenced by testDebug().

◆ triggerException()

Fault gem5::SelfDebug::triggerException ( ThreadContext * tc,
Addr vaddr )
protected

Definition at line 108 of file self_debug.cc.

References gem5::ArmISA::ArmFault::BRKPOINT, gem5::ArmISA::ArmFault::DebugEvent, to32, gem5::ArmISA::UnknownTran, and gem5::MipsISA::vaddr.

Referenced by testBreakPoints().

◆ triggerWatchpointException()

Fault gem5::SelfDebug::triggerWatchpointException ( ThreadContext * tc,
Addr vaddr,
bool write,
bool cm )
protected

Definition at line 141 of file self_debug.cc.

References gem5::ArmISA::cm, gem5::ArmISA::d, gem5::ArmISA::ArmFault::DebugEvent, gem5::ArmISA::NoAccess, to32, gem5::ArmISA::UnknownTran, gem5::MipsISA::vaddr, gem5::ArmISA::ArmFault::WPOINT_CM, and gem5::ArmISA::ArmFault::WPOINT_NOCM.

Referenced by testWatchPoints().

◆ updateDBGBCR()

void gem5::ArmISA::SelfDebug::updateDBGBCR ( int index,
DBGBCR val )
inline

Definition at line 368 of file self_debug.hh.

References arBrkPoints, gem5::MipsISA::index, and gem5::X86ISA::val.

◆ updateDBGWCR()

void gem5::ArmISA::SelfDebug::updateDBGWCR ( int index,
DBGWCR val )
inline

Definition at line 374 of file self_debug.hh.

References arWatchPoints, gem5::MipsISA::index, and gem5::X86ISA::val.

◆ updateOSLock()

void gem5::ArmISA::SelfDebug::updateOSLock ( RegVal val)
inline

Definition at line 362 of file self_debug.hh.

References gem5::bits(), oslk, and gem5::X86ISA::val.

Referenced by init().

Member Data Documentation

◆ aarch32

bool gem5::ArmISA::SelfDebug::aarch32
private

Definition at line 255 of file self_debug.hh.

Referenced by init(), isAArch32(), isDebugEnabled(), setAArch32(), and targetAArch32().

◆ arBrkPoints

std::vector<BrkPoint> gem5::ArmISA::SelfDebug::arBrkPoints
private

Definition at line 244 of file self_debug.hh.

Referenced by activateDebug(), getBrkPoint(), init(), testBreakPoints(), and updateDBGBCR().

◆ arWatchPoints

std::vector<WatchPoint> gem5::ArmISA::SelfDebug::arWatchPoints
private

Definition at line 245 of file self_debug.hh.

Referenced by init(), testWatchPoints(), and updateDBGWCR().

◆ enableTdeTge

bool gem5::ArmISA::SelfDebug::enableTdeTge
private

Definition at line 248 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), SelfDebug(), and setenableTDETGE().

◆ kde

bool gem5::ArmISA::SelfDebug::kde
private

Definition at line 252 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), SelfDebug(), and setMDSCRvals().

◆ mde

bool gem5::ArmISA::SelfDebug::mde
private

Definition at line 250 of file self_debug.hh.

Referenced by enabled(), SelfDebug(), setMDBGen(), setMDSCRvals(), testBreakPoints(), and testWatchPoints().

◆ oslk

bool gem5::ArmISA::SelfDebug::oslk
private

Definition at line 253 of file self_debug.hh.

Referenced by isDebugEnabledForEL32(), isDebugEnabledForEL64(), SelfDebug(), and updateOSLock().

◆ sdd

bool gem5::ArmISA::SelfDebug::sdd
private

Definition at line 251 of file self_debug.hh.

Referenced by isDebugEnabledForEL64(), SelfDebug(), and setbSDD().

◆ softStep

SoftwareStep* gem5::ArmISA::SelfDebug::softStep
private

Definition at line 246 of file self_debug.hh.

Referenced by enabled(), getSstep(), SelfDebug(), setDebugMask(), setMDSCRvals(), testDebug(), and ~SelfDebug().

◆ to32

bool gem5::ArmISA::SelfDebug::to32
private

Definition at line 256 of file self_debug.hh.

Referenced by testBreakPoints(), testWatchPoints(), triggerException(), and triggerWatchpointException().

The documentation for this class was generated from the following files:
Generated on Mon May 26 2025 09:19:29 for gem5 by doxygen 1.13.2