gem5::VegaISA::PackedReg< BITS, ELEM_SIZE > Class Template Reference

#include <operand.hh>

Public Member Functions
	PackedReg ()=default
void	setDword (int dw, uint32_t value)
uint32_t	getDword (int dw)
uint32_t	getElem (int elem)
void	setElem (int elem, uint32_t value)

Private Attributes
uint32_t	dwords [NumDwords] = {}

Static Private Attributes
static constexpr int	NumDwords = BITS / 32

Detailed Description

template<int BITS, int ELEM_SIZE>
class gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >

Definition at line 859 of file operand.hh.

Constructor & Destructor Documentation

PackedReg()

template<int BITS, int ELEM_SIZE>

gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::PackedReg ( )

default

Member Function Documentation

getDword()

template<int BITS, int ELEM_SIZE>

uint32_t gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::getDword ( int dw )

inline

Definition at line 885 of file operand.hh.

References dwords, and NumDwords.

Referenced by gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_PK32< AMDGPU::mxbfloat16, AMDGPU::mxbf6, &MNEM__V_CVT_SCALEF32_PK32_BF16_BF6 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_SR_PK32< AMDGPU::mxbf6, AMDGPU::mxbfloat16, &MNEM__V_CVT_SCALE_SR_PK_BF6_BF16 >::execute(), and gem5::VegaISA::Inst_VOP3__V_CVT_SCALEF32_2XPK16_F32< AMDGPU::mxbf6, AMDGPU::mxfloat32, &MNEM__V_CVT_SCALEF32_PK32_BF6_F32 >::execute().

getElem()

template<int BITS, int ELEM_SIZE>

uint32_t gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::getElem ( int elem )

inline

Definition at line 892 of file operand.hh.

References dwords, and gem5::RiscvISA::elem_mask().

Referenced by gem5::VegaISA::Inst_DS__DS_READ_B96_TR_B6::completeAcc(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_PK32< AMDGPU::mxbfloat16, AMDGPU::mxbf6, &MNEM__V_CVT_SCALEF32_PK32_BF16_BF6 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_SR_PK32< AMDGPU::mxbf6, AMDGPU::mxbfloat16, &MNEM__V_CVT_SCALE_SR_PK_BF6_BF16 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALEF32_2XPK16_F32< AMDGPU::mxbf6, AMDGPU::mxfloat32, &MNEM__V_CVT_SCALEF32_PK32_BF6_F32 >::execute(), and gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< 16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8 >::execute().

setDword()

template<int BITS, int ELEM_SIZE>

void gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::setDword ( int dw, uint32_t value )

inline

Definition at line 878 of file operand.hh.

References dwords, and NumDwords.

Referenced by gem5::VegaISA::Inst_DS__DS_READ_B96_TR_B6::completeAcc(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_PK32< AMDGPU::mxbfloat16, AMDGPU::mxbf6, &MNEM__V_CVT_SCALEF32_PK32_BF16_BF6 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_SR_PK32< AMDGPU::mxbf6, AMDGPU::mxbfloat16, &MNEM__V_CVT_SCALE_SR_PK_BF6_BF16 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALEF32_2XPK16_F32< AMDGPU::mxbf6, AMDGPU::mxfloat32, &MNEM__V_CVT_SCALEF32_PK32_BF6_F32 >::execute(), and gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< 16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8 >::execute().

setElem()

template<int BITS, int ELEM_SIZE>

void gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::setElem ( int elem, uint32_t value )

inline

Definition at line 933 of file operand.hh.

References dwords, gem5::RiscvISA::elem_mask(), and gem5::ArmISA::mask.

Referenced by gem5::VegaISA::Inst_DS__DS_READ_B96_TR_B6::completeAcc(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_PK32< AMDGPU::mxbfloat16, AMDGPU::mxbf6, &MNEM__V_CVT_SCALEF32_PK32_BF16_BF6 >::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_SCALE_SR_PK32< AMDGPU::mxbf6, AMDGPU::mxbfloat16, &MNEM__V_CVT_SCALE_SR_PK_BF6_BF16 >::execute(), and gem5::VegaISA::Inst_VOP3__V_CVT_SCALEF32_2XPK16_F32< AMDGPU::mxbf6, AMDGPU::mxfloat32, &MNEM__V_CVT_SCALEF32_PK32_BF6_F32 >::execute().

Member Data Documentation

dwords

template<int BITS, int ELEM_SIZE>

uint32_t gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::dwords[NumDwords] = {}

private

Definition at line 872 of file operand.hh.

Referenced by getDword(), getElem(), setDword(), and setElem().

NumDwords

template<int BITS, int ELEM_SIZE>

int gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::NumDwords = BITS / 32

staticconstexprprivate

Definition at line 871 of file operand.hh.

Referenced by getDword(), and setDword().

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The documentation for this class was generated from the following file:

• arch/amdgpu/vega/operand.hh