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gem5 [DEVELOP-FOR-25.1]
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#include <cstring>#include <vector>#include "dev/dma_device.hh"#include "dev/pci/pcireg.h"#include "dev/pci/types.hh"#include "dev/pci/upstream.hh"#include "params/PciBar.hh"#include "params/PciBarNone.hh"#include "params/PciDevice.hh"#include "params/PciEndpoint.hh"#include "params/PciIoBar.hh"#include "params/PciLegacyIoBar.hh"#include "params/PciMemBar.hh"#include "params/PciMemUpperBar.hh"#include "params/PciType1Device.hh"#include "sim/byteswap.hh"Go to the source code of this file.
Classes | |
| class | gem5::PciBar |
| class | gem5::PciBarNone |
| class | gem5::PciIoBar |
| class | gem5::PciLegacyIoBar |
| class | gem5::PciMemBar |
| class | gem5::PciMemUpperBar |
| class | gem5::PciDevice |
| Base class to represent a PCI device. More... | |
| class | gem5::PciEndpoint |
| PCI type 0 device class to represent any PCI endpoint, like a GPU, a network card and so on. More... | |
| class | gem5::PciType1Device |
| PCI type 1 device class to represent any PCI bridge to extend the PCI hierarchy with a new bus. More... | |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
Macros | |
| #define | PCI0_BAR_NUMBER(x) |
| #define | PCI1_BAR_NUMBER(x) |
| #define PCI0_BAR_NUMBER | ( | x | ) |
Definition at line 66 of file device.hh.
Referenced by gem5::PciEndpoint::writeConfig().
| #define PCI1_BAR_NUMBER | ( | x | ) |
Definition at line 67 of file device.hh.
Referenced by gem5::PciType1Device::writeConfig().