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gem5 [DEVELOP-FOR-25.0]
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Implementation of a GICv2. More...
#include <vector>#include "arch/arm/interrupts.hh"#include "base/addr_range.hh"#include "base/bitunion.hh"#include "dev/arm/base_gic.hh"#include "dev/io_device.hh"#include "dev/platform.hh"#include "params/GicV2.hh"Go to the source code of this file.
Classes | |
| class | gem5::GicV2Registers |
| class | gem5::GicV2 |
| struct | gem5::GicV2::BankedRegs |
| Registers "banked for each connected processor" per ARM IHI0048B. More... | |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
Implementation of a GICv2.
Definition in file gic_v2.hh.