gem5 [DEVELOP-FOR-25.0]
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ltage.cc
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1/*
2 * Copyright (c) 2022-2023 The University of Edinburgh
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2014 The University of Wisconsin
15 *
16 * Copyright (c) 2006 INRIA (Institut National de Recherche en
17 * Informatique et en Automatique / French National Research Institute
18 * for Computer Science and Applied Mathematics)
19 *
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46/* @file
47 * Implementation of a L-TAGE branch predictor
48 */
49
50#include "cpu/pred/ltage.hh"
51
52#include "base/intmath.hh"
53#include "base/logging.hh"
54#include "base/trace.hh"
55#include "debug/Fetch.hh"
56#include "debug/LTage.hh"
57
58namespace gem5
59{
60
61namespace branch_prediction
62{
63
64LTAGE::LTAGE(const LTAGEParams &params)
65 : TAGE(params), loopPredictor(params.loop_predictor)
66{
67}
68
69void
71{
72 TAGE::init();
73}
74
75void
77 bool uncond, void * &bpHistory)
78{
80 pc, !uncond);
81 bpHistory = (void*)(bi);
82}
83
84//prediction
85bool
86LTAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b)
87{
89 branch_pc, cond_branch);
90 b = (void*)(bi);
91
92 bool pred_taken = tage->tagePredict(tid, branch_pc, cond_branch,
93 bi->tageBranchInfo);
94
95 pred_taken = loopPredictor->loopPredict(tid, branch_pc, cond_branch,
96 bi->lpBranchInfo, pred_taken,
98 if (cond_branch) {
99 if (bi->lpBranchInfo->loopPredUsed) {
100 bi->tageBranchInfo->provider = LOOP;
101 }
102 DPRINTF(LTage, "Predict for %lx: taken?:%d, loopTaken?:%d, "
103 "loopValid?:%d, loopUseCounter:%d, tagePred:%d, altPred:%d\n",
104 branch_pc, pred_taken, bi->lpBranchInfo->loopPred,
105 bi->lpBranchInfo->loopPredValid,
106 loopPredictor->getLoopUseCounter(),
107 bi->tageBranchInfo->tagePred, bi->tageBranchInfo->altTaken);
108 }
109
110 // record final prediction
111 bi->lpBranchInfo->predTaken = pred_taken;
112
113 return pred_taken;
114}
115
116// PREDICTOR UPDATE
117void
118LTAGE::update(ThreadID tid, Addr pc, bool taken, void * &bp_history,
119 bool squashed, const StaticInstPtr & inst, Addr target)
120{
121 assert(bp_history);
122
123 LTageBranchInfo* bi = static_cast<LTageBranchInfo*>(bp_history);
124
125 if (squashed) {
126 if (tage->isSpeculativeUpdateEnabled()) {
127 // This restores the global history, then update it
128 // and recomputes the folded histories.
129 tage->squash(tid, taken, target, inst, bi->tageBranchInfo);
130
131 if (bi->tageBranchInfo->condBranch) {
132 loopPredictor->squashLoop(bi->lpBranchInfo);
133 }
134 }
135 return;
136 }
137
138 int nrand = rng->random<int>() & 3;
139 if (bi->tageBranchInfo->condBranch) {
140 DPRINTF(LTage, "Updating tables for branch:%lx; taken?:%d\n",
141 pc, taken);
142 tage->updateStats(taken, bi->tageBranchInfo);
143
144 loopPredictor->updateStats(taken, bi->lpBranchInfo);
145
146 loopPredictor->condBranchUpdate(tid, pc, taken,
147 bi->tageBranchInfo->tagePred, bi->lpBranchInfo, instShiftAmt);
148
149 tage->condBranchUpdate(tid, pc, taken, bi->tageBranchInfo,
150 nrand, target, bi->lpBranchInfo->predTaken);
151 }
152
153 tage->updateHistories(tid, pc, false, taken, target,
154 inst, bi->tageBranchInfo);
155
156 delete bi;
157 bp_history = nullptr;
158}
159
160void
161LTAGE::squash(ThreadID tid, void * &bp_history)
162{
163 LTageBranchInfo* bi = (LTageBranchInfo*)(bp_history);
164
165 if (bi->tageBranchInfo->condBranch) {
166 loopPredictor->squash(tid, bi->lpBranchInfo);
167 }
168
169 TAGE::squash(tid, bp_history);
170}
171
172} // namespace branch_prediction
173} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
const unsigned instShiftAmt
Number of bits to shift instructions by for predictor addresses.
void update(ThreadID tid, Addr pc, bool taken, void *&bp_history, bool squashed, const StaticInstPtr &inst, Addr target) override
Updates the BP with taken/not taken information.
Definition ltage.cc:118
void branchPlaceholder(ThreadID tid, Addr pc, bool uncond, void *&bp_history) override
Special function for the decoupled front-end.
Definition ltage.cc:76
LTAGE(const LTAGEParams &params)
Definition ltage.cc:64
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition ltage.cc:70
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition ltage.cc:86
LoopPredictor * loopPredictor
The loop predictor object.
Definition ltage.hh:94
void squash(ThreadID tid, void *&bp_history) override
Definition ltage.cc:161
Random::RandomPtr rng
Definition tage.hh:82
TAGE(const TAGEParams &params)
Definition tage.cc:65
void squash(ThreadID tid, void *&bp_history) override
Definition tage.cc:102
const Params & params() const
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition sim_object.cc:73
Bitfield< 7 > b
Bitfield< 4 > pc
Bitfield< 20, 16 > bi
Definition types.hh:80
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
RefCountingPtr< StaticInst > StaticInstPtr

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