gem5
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arch
arm
insts
mult.hh
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_INSTS_MULT_HH__
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#define __ARCH_ARM_INSTS_MULT_HH__
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#include "
arch/arm/insts/static_inst.hh
"
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#include "
base/trace.hh
"
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namespace
gem5
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{
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namespace
ArmISA
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{
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class
Mult3
:
public
PredOp
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{
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protected
:
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RegIndex
reg0
,
reg1
,
reg2
;
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Mult3
(
const
char
*mnem,
ExtMachInst
_machInst, OpClass __opClass,
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RegIndex
_reg0,
RegIndex
_reg1,
RegIndex
_reg2) :
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PredOp
(mnem, _machInst, __opClass),
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reg0
(_reg0),
reg1
(_reg1),
reg2
(_reg2)
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{}
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};
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class
Mult4
:
public
Mult3
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{
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protected
:
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RegIndex
reg3
;
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Mult4
(
const
char
*mnem,
ExtMachInst
_machInst, OpClass __opClass,
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RegIndex
_reg0,
RegIndex
_reg1,
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RegIndex
_reg2,
RegIndex
_reg3) :
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Mult3
(mnem, _machInst, __opClass, _reg0, _reg1, _reg2),
reg3
(_reg3)
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{}
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};
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}
// namespace ArmISA
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}
// namespace gem5
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#endif
//__ARCH_ARM_INSTS_MULT_HH__
static_inst.hh
trace.hh
gem5::ArmISA::Mult3::Mult3
Mult3(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _reg0, RegIndex _reg1, RegIndex _reg2)
Definition
mult.hh:58
gem5::ArmISA::Mult3::reg2
RegIndex reg2
Definition
mult.hh:56
gem5::ArmISA::Mult3::reg0
RegIndex reg0
Definition
mult.hh:56
gem5::ArmISA::Mult3::reg1
RegIndex reg1
Definition
mult.hh:56
gem5::ArmISA::Mult4::reg3
RegIndex reg3
Definition
mult.hh:71
gem5::ArmISA::Mult4::Mult4
Mult4(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _reg0, RegIndex _reg1, RegIndex _reg2, RegIndex _reg3)
Definition
mult.hh:73
gem5::ArmISA::PredOp::PredOp
PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition
pred_inst.hh:223
gem5::ArmISA
Definition
decoder.cc:54
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
gem5::RegIndex
uint16_t RegIndex
Definition
types.hh:176
gem5::X86ISA::ExtMachInst
Definition
types.hh:213
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