gem5 [DEVELOP-FOR-25.1]
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pl111.cc
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1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "dev/arm/pl111.hh"
39
40#include "base/output.hh"
41#include "base/trace.hh"
42#include "base/vnc/vncinput.hh"
43#include "debug/PL111.hh"
44#include "debug/Uart.hh"
46#include "dev/arm/base_gic.hh"
47#include "mem/packet.hh"
48#include "mem/packet_access.hh"
49#include "params/Pl111.hh"
50#include "sim/system.hh"
51
52// clang complains about std::set being overloaded with Packet::set if
53// we open up the entire namespace std
54using std::vector;
55
56namespace gem5
57{
58
59// initialize clcd registers
61 : AmbaDmaDevice(p, 0x10000), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
63 lcdRis(0), lcdMis(0),
67 pixelClock(p.pixel_clock),
69 vnc(p.vnc), bmp(&fb), pic(NULL),
73 readEvent([this]{ readFramebuffer(); }, name()),
74 fillFifoEvent([this]{ fillFifo(); }, name()),
75 dmaDoneEventAll(maxOutstandingDma, this),
76 dmaDoneEventFree(maxOutstandingDma),
77 intEvent([this]{ generateInterrupt(); }, name()),
78 enableCapture(p.enable_capture)
79{
80 dmaBuffer = new uint8_t[buffer_size];
81
82 memset(lcdPalette, 0, sizeof(lcdPalette));
83 memset(cursorImage, 0, sizeof(cursorImage));
84 memset(dmaBuffer, 0, buffer_size);
85
86 for (int i = 0; i < maxOutstandingDma; ++i)
87 dmaDoneEventFree[i] = &dmaDoneEventAll[i];
88
89 if (vnc)
90 vnc->setFrameBuffer(&fb);
91}
92
94{
95 delete[] dmaBuffer;
96}
97
98// read registers and frame buffer
99Tick
101{
102 // use a temporary data since the LCD registers are read/written with
103 // different size operations
104
105 uint32_t data = 0;
106
107 assert(pkt->getAddr() >= pioAddr &&
108 pkt->getAddr() < pioAddr + pioSize);
109
110 Addr daddr = pkt->getAddr() - pioAddr;
111
112 DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize());
113
114 switch (daddr) {
115 case LcdTiming0:
117 break;
118 case LcdTiming1:
120 break;
121 case LcdTiming2:
123 break;
124 case LcdTiming3:
126 break;
127 case LcdUpBase:
128 data = lcdUpbase;
129 break;
130 case LcdLpBase:
131 data = lcdLpbase;
132 break;
133 case LcdControl:
135 break;
136 case LcdImsc:
137 data = lcdImsc;
138 break;
139 case LcdRis:
140 data = lcdRis;
141 break;
142 case LcdMis:
143 data = lcdMis;
144 break;
145 case LcdIcr:
146 panic("LCD register at offset %#x is Write-Only\n", daddr);
147 break;
148 case LcdUpCurr:
149 data = curAddr;
150 break;
151 case LcdLpCurr:
152 data = curAddr;
153 break;
154 case ClcdCrsrCtrl:
156 break;
157 case ClcdCrsrConfig:
159 break;
160 case ClcdCrsrPalette0:
162 break;
163 case ClcdCrsrPalette1:
165 break;
166 case ClcdCrsrXY:
168 break;
169 case ClcdCrsrClip:
171 break;
172 case ClcdCrsrImsc:
174 break;
175 case ClcdCrsrIcr:
176 panic("CLCD register at offset %#x is Write-Only\n", daddr);
177 break;
178 case ClcdCrsrRis:
180 break;
181 case ClcdCrsrMis:
183 break;
184 default:
185 if (readId(pkt, AMBA_ID, pioAddr)) {
186 // Hack for variable size accesses
187 data = pkt->getUintX(ByteOrder::little);
188 break;
189 } else if (daddr >= CrsrImage && daddr <= 0xBFC) {
190 // CURSOR IMAGE
191 int index;
192 index = (daddr - CrsrImage) >> 2;
194 break;
195 } else if (daddr >= LcdPalette && daddr <= 0x3FC) {
196 // LCD Palette
197 int index;
198 index = (daddr - LcdPalette) >> 2;
200 break;
201 } else {
202 panic("Tried to read CLCD register at offset %#x that "
203 "doesn't exist\n", daddr);
204 break;
205 }
206 }
207
208 pkt->setUintX(data, ByteOrder::little);
209 pkt->makeAtomicResponse();
210 return pioDelay;
211}
212
213// write registers and frame buffer
214Tick
216{
217 // use a temporary data since the LCD registers are read/written with
218 // different size operations
219 //
220 const uint32_t data = pkt->getUintX(ByteOrder::little);
221
222 assert(pkt->getAddr() >= pioAddr &&
223 pkt->getAddr() < pioAddr + pioSize);
224
225 Addr daddr = pkt->getAddr() - pioAddr;
226
227 DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr,
228 pkt->getLE<uint8_t>(), pkt->getSize());
229
230 switch (daddr) {
231 case LcdTiming0:
233 // width = 16 * (PPL+1)
234 width = (lcdTiming0.ppl + 1) << 4;
235 break;
236 case LcdTiming1:
238 // height = LPP + 1
239 height = (lcdTiming1.lpp) + 1;
240 break;
241 case LcdTiming2:
243 break;
244 case LcdTiming3:
246 break;
247 case LcdUpBase:
248 lcdUpbase = data;
249 DPRINTF(PL111, "####### Upper panel base set to: %#x #######\n", lcdUpbase);
250 break;
251 case LcdLpBase:
252 warn_once("LCD dual screen mode not supported\n");
253 lcdLpbase = data;
254 DPRINTF(PL111, "###### Lower panel base set to: %#x #######\n", lcdLpbase);
255 break;
256 case LcdControl:
257 int old_lcdpwr;
258 old_lcdpwr = lcdControl.lcdpwr;
260
261 DPRINTF(PL111, "LCD power is:%d\n", lcdControl.lcdpwr);
262
263 // LCD power enable
264 if (lcdControl.lcdpwr && !old_lcdpwr) {
266 DPRINTF(PL111, " lcd size: height %d width %d\n", height, width);
267 waterMark = lcdControl.watermark ? 8 : 4;
268 startDma();
269 }
270 break;
271 case LcdImsc:
272 lcdImsc = data;
273 if (lcdImsc.vcomp)
274 panic("Interrupting on vcomp not supported\n");
275
277
278 if (!lcdMis)
279 interrupt->clear();
280
281 break;
282 case LcdRis:
283 panic("LCD register at offset %#x is Read-Only\n", daddr);
284 break;
285 case LcdMis:
286 panic("LCD register at offset %#x is Read-Only\n", daddr);
287 break;
288 case LcdIcr:
289 lcdRis = lcdRis & ~data;
291
292 if (!lcdMis)
293 interrupt->clear();
294
295 break;
296 case LcdUpCurr:
297 panic("LCD register at offset %#x is Read-Only\n", daddr);
298 break;
299 case LcdLpCurr:
300 panic("LCD register at offset %#x is Read-Only\n", daddr);
301 break;
302 case ClcdCrsrCtrl:
304 break;
305 case ClcdCrsrConfig:
307 break;
308 case ClcdCrsrPalette0:
310 break;
311 case ClcdCrsrPalette1:
313 break;
314 case ClcdCrsrXY:
316 break;
317 case ClcdCrsrClip:
319 break;
320 case ClcdCrsrImsc:
322 break;
323 case ClcdCrsrIcr:
325 break;
326 case ClcdCrsrRis:
327 panic("CLCD register at offset %#x is Read-Only\n", daddr);
328 break;
329 case ClcdCrsrMis:
330 panic("CLCD register at offset %#x is Read-Only\n", daddr);
331 break;
332 default:
333 if (daddr >= CrsrImage && daddr <= 0xBFC) {
334 // CURSOR IMAGE
335 int index;
336 index = (daddr - CrsrImage) >> 2;
338 break;
339 } else if (daddr >= LcdPalette && daddr <= 0x3FC) {
340 // LCD Palette
341 int index;
342 index = (daddr - LcdPalette) >> 2;
344 break;
345 } else {
346 panic("Tried to write PL111 register at offset %#x that "
347 "doesn't exist\n", daddr);
348 break;
349 }
350 }
351
352 pkt->makeAtomicResponse();
353 return pioDelay;
354}
355
358{
359 unsigned rw, gw, bw;
360 unsigned offsets[3];
361
362 switch (lcdControl.lcdbpp) {
363 case bpp24:
364 rw = gw = bw = 8;
365 offsets[0] = 0;
366 offsets[1] = 8;
367 offsets[2] = 16;
368 break;
369
370 case bpp16m565:
371 rw = 5;
372 gw = 6;
373 bw = 5;
374 offsets[0] = 0;
375 offsets[1] = 5;
376 offsets[2] = 11;
377 break;
378
379 default:
380 panic("Unimplemented video mode\n");
381 }
382
383 if (lcdControl.bgr) {
384 return PixelConverter(
386 offsets[2], offsets[1], offsets[0],
387 rw, gw, bw,
388 ByteOrder::little);
389 } else {
390 return PixelConverter(
392 offsets[0], offsets[1], offsets[2],
393 rw, gw, bw,
394 ByteOrder::little);
395 }
396}
397
398void
400{
401 if (lcdControl.lcdbpp == bpp24) {
402 bytesPerPixel = 4;
403 } else if (lcdControl.lcdbpp == bpp16m565) {
404 bytesPerPixel = 2;
405 }
406
407 fb.resize(width, height);
409
410 // Workaround configuration bugs where multiple display
411 // controllers are attached to the same VNC server by reattaching
412 // enabled devices. This isn't ideal, but works as long as only
413 // one display controller is active at a time.
414 if (lcdControl.lcdpwr && vnc)
415 vnc->setFrameBuffer(&fb);
416}
417
418void
420{
421 if (dmaPendingNum != 0 || readEvent.scheduled())
422 return;
424}
425
426void
428{
429 // initialization for dma read from frame buffer to dma buffer
430 uint32_t length = height * width;
431 if (startAddr != lcdUpbase)
433
434 // Updating base address, interrupt if we're supposed to
435 lcdRis.baseaddr = 1;
436 if (!intEvent.scheduled())
438
439 curAddr = 0;
440 startTime = curTick();
441
442 maxAddr = static_cast<Addr>(length * bytesPerPixel);
443
444 DPRINTF(PL111, " lcd frame buffer size of %d bytes \n", maxAddr);
445
446 fillFifo();
447}
448
449void
451{
452 while ((dmaPendingNum < maxOutstandingDma) && (maxAddr >= curAddr + dmaSize )) {
453 // concurrent dma reads need different dma done events
454 // due to assertion in scheduling state
456
457 assert(!dmaDoneEventFree.empty());
458 DmaDoneEvent *event(dmaDoneEventFree.back());
459 dmaDoneEventFree.pop_back();
460 assert(!event->scheduled());
461
462 // We use a uncachable request here because the requests from the CPU
463 // will be uncacheable as well. If we have uncacheable and cacheable
464 // requests in the memory system for the same address it won't be
465 // pleased
469 curAddr += dmaSize;
470 }
471}
472
473void
475{
476 DPRINTF(PL111, "DMA Done\n");
477
478 Tick maxFrameTime = lcdTiming2.cpl * height * pixelClock;
479
481
482 if (maxAddr == curAddr && !dmaPendingNum) {
483 if ((curTick() - startTime) > maxFrameTime) {
484 warn("CLCD controller buffer underrun, took %d ticks when should"
485 " have taken %d\n", curTick() - startTime, maxFrameTime);
486 lcdRis.underflow = 1;
487 if (!intEvent.scheduled())
489 }
490
491 assert(!readEvent.scheduled());
492 fb.copyIn(dmaBuffer, converter);
493 if (vnc)
494 vnc->setDirty();
495
496 if (enableCapture) {
497 DPRINTF(PL111, "-- write out frame buffer into bmp\n");
498
499 if (!pic)
500 pic = simout.create(csprintf("%s.framebuffer.bmp", sys->name()),
501 true);
502
503 assert(pic);
504 pic->stream()->seekp(0);
505 bmp.write(*pic->stream());
506 }
507
508 // schedule the next read based on when the last frame started
509 // and the desired fps (i.e. maxFrameTime), we turn the
510 // argument into a relative number of cycles in the future
511 if (lcdControl.lcden)
513 curTick() +
514 maxFrameTime)));
515 }
516
518 return;
519
520 if (!fillFifoEvent.scheduled())
522}
523
524void
526{
527 DPRINTF(PL111, "Serializing ARM PL111\n");
528
529 uint32_t lcdTiming0_serial = lcdTiming0;
530 SERIALIZE_SCALAR(lcdTiming0_serial);
531
532 uint32_t lcdTiming1_serial = lcdTiming1;
533 SERIALIZE_SCALAR(lcdTiming1_serial);
534
535 uint32_t lcdTiming2_serial = lcdTiming2;
536 SERIALIZE_SCALAR(lcdTiming2_serial);
537
538 uint32_t lcdTiming3_serial = lcdTiming3;
539 SERIALIZE_SCALAR(lcdTiming3_serial);
540
543
544 uint32_t lcdControl_serial = lcdControl;
545 SERIALIZE_SCALAR(lcdControl_serial);
546
547 uint8_t lcdImsc_serial = lcdImsc;
548 SERIALIZE_SCALAR(lcdImsc_serial);
549
550 uint8_t lcdRis_serial = lcdRis;
551 SERIALIZE_SCALAR(lcdRis_serial);
552
553 uint8_t lcdMis_serial = lcdMis;
554 SERIALIZE_SCALAR(lcdMis_serial);
555
558
565
566 uint8_t clcdCrsrImsc_serial = clcdCrsrImsc;
567 SERIALIZE_SCALAR(clcdCrsrImsc_serial);
568
569 uint8_t clcdCrsrIcr_serial = clcdCrsrIcr;
570 SERIALIZE_SCALAR(clcdCrsrIcr_serial);
571
572 uint8_t clcdCrsrRis_serial = clcdCrsrRis;
573 SERIALIZE_SCALAR(clcdCrsrRis_serial);
574
575 uint8_t clcdCrsrMis_serial = clcdCrsrMis;
576 SERIALIZE_SCALAR(clcdCrsrMis_serial);
577
581
589
590 Tick int_event_time = 0;
591 Tick read_event_time = 0;
592 Tick fill_fifo_event_time = 0;
593
594 if (readEvent.scheduled())
595 read_event_time = readEvent.when();
596 if (fillFifoEvent.scheduled())
597 fill_fifo_event_time = fillFifoEvent.when();
598 if (intEvent.scheduled())
599 int_event_time = intEvent.when();
600
601 SERIALIZE_SCALAR(read_event_time);
602 SERIALIZE_SCALAR(fill_fifo_event_time);
603 SERIALIZE_SCALAR(int_event_time);
604
605 vector<Tick> dma_done_event_tick;
606 dma_done_event_tick.resize(maxOutstandingDma);
607 for (int x = 0; x < maxOutstandingDma; x++) {
608 dma_done_event_tick[x] = dmaDoneEventAll[x].scheduled() ?
609 dmaDoneEventAll[x].when() : 0;
610 }
611 SERIALIZE_CONTAINER(dma_done_event_tick);
612}
613
614void
616{
617 DPRINTF(PL111, "Unserializing ARM PL111\n");
618
619 uint32_t lcdTiming0_serial;
620 UNSERIALIZE_SCALAR(lcdTiming0_serial);
621 lcdTiming0 = lcdTiming0_serial;
622
623 uint32_t lcdTiming1_serial;
624 UNSERIALIZE_SCALAR(lcdTiming1_serial);
625 lcdTiming1 = lcdTiming1_serial;
626
627 uint32_t lcdTiming2_serial;
628 UNSERIALIZE_SCALAR(lcdTiming2_serial);
629 lcdTiming2 = lcdTiming2_serial;
630
631 uint32_t lcdTiming3_serial;
632 UNSERIALIZE_SCALAR(lcdTiming3_serial);
633 lcdTiming3 = lcdTiming3_serial;
634
637
638 uint32_t lcdControl_serial;
639 UNSERIALIZE_SCALAR(lcdControl_serial);
640 lcdControl = lcdControl_serial;
641
642 uint8_t lcdImsc_serial;
643 UNSERIALIZE_SCALAR(lcdImsc_serial);
644 lcdImsc = lcdImsc_serial;
645
646 uint8_t lcdRis_serial;
647 UNSERIALIZE_SCALAR(lcdRis_serial);
648 lcdRis = lcdRis_serial;
649
650 uint8_t lcdMis_serial;
651 UNSERIALIZE_SCALAR(lcdMis_serial);
652 lcdMis = lcdMis_serial;
653
656
663
664 uint8_t clcdCrsrImsc_serial;
665 UNSERIALIZE_SCALAR(clcdCrsrImsc_serial);
666 clcdCrsrImsc = clcdCrsrImsc_serial;
667
668 uint8_t clcdCrsrIcr_serial;
669 UNSERIALIZE_SCALAR(clcdCrsrIcr_serial);
670 clcdCrsrIcr = clcdCrsrIcr_serial;
671
672 uint8_t clcdCrsrRis_serial;
673 UNSERIALIZE_SCALAR(clcdCrsrRis_serial);
674 clcdCrsrRis = clcdCrsrRis_serial;
675
676 uint8_t clcdCrsrMis_serial;
677 UNSERIALIZE_SCALAR(clcdCrsrMis_serial);
678 clcdCrsrMis = clcdCrsrMis_serial;
679
683
691
692 Tick int_event_time = 0;
693 Tick read_event_time = 0;
694 Tick fill_fifo_event_time = 0;
695
696 UNSERIALIZE_SCALAR(read_event_time);
697 UNSERIALIZE_SCALAR(fill_fifo_event_time);
698 UNSERIALIZE_SCALAR(int_event_time);
699
700 if (int_event_time)
701 schedule(intEvent, int_event_time);
702 if (read_event_time)
703 schedule(readEvent, read_event_time);
704 if (fill_fifo_event_time)
705 schedule(fillFifoEvent, fill_fifo_event_time);
706
707 vector<Tick> dma_done_event_tick;
708 dma_done_event_tick.resize(maxOutstandingDma);
709 UNSERIALIZE_CONTAINER(dma_done_event_tick);
710 dmaDoneEventFree.clear();
711 for (int x = 0; x < maxOutstandingDma; x++) {
712 if (dma_done_event_tick[x])
713 schedule(dmaDoneEventAll[x], dma_done_event_tick[x]);
714 else
716 }
718
719 if (lcdControl.lcdpwr) {
721 fb.copyIn(dmaBuffer, converter);
722 if (vnc)
723 vnc->setDirty();
724 }
725}
726
727void
729{
730 DPRINTF(PL111, "Generate Interrupt: lcdImsc=0x%x lcdRis=0x%x lcdMis=0x%x\n",
731 (uint32_t)lcdImsc, (uint32_t)lcdRis, (uint32_t)lcdMis);
733
734 if (lcdMis.underflow || lcdMis.baseaddr || lcdMis.vcomp || lcdMis.ahbmaster) {
735 interrupt->raise();
736 DPRINTF(PL111, " -- Generated\n");
737 }
738}
739
742{
743 AddrRangeList ranges;
744 ranges.push_back(RangeSize(pioAddr, pioSize));
745 return ranges;
746}
747
748} // namespace gem5
This is a base class for AMBA devices that have to respond to Device and Implementer ID calls.
#define DPRINTF(x,...)
Definition trace.hh:209
Base class for ARM GIC implementations.
const char data[]
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
ArmInterruptPin *const interrupt
AmbaDmaDevice(const Params &p, Addr pio_size=0)
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles ticksToCycles(Tick t) const
Addr getAddr() const
Definition packet.hh:807
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition packet.cc:361
unsigned getSize() const
Definition packet.hh:817
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition packet.cc:352
void makeAtomicResponse()
Definition packet.hh:1074
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Configurable RGB pixel converter.
Definition pixel.hh:92
void dmaDone()
DMA done event.
Definition pl111.cc:474
static const int LcdLpCurr
Definition pl111.hh:79
static const int ClcdCrsrCtrl
Definition pl111.hh:82
Addr curAddr
Frame buffer current address.
Definition pl111.hh:298
EventFunctionWrapper readEvent
DMA framebuffer read event.
Definition pl111.hh:330
static const int ClcdCrsrXY
Definition pl111.hh:86
uint32_t clcdCrsrClip
Cursor clip position register.
Definition pl111.hh:247
Addr startAddr
Frame buffer base address.
Definition pl111.hh:292
ControlReg lcdControl
Control register.
Definition pl111.hh:214
static const int LcdMaxWidth
Definition pl111.hh:96
uint32_t clcdCrsrXY
Cursor XY position register.
Definition pl111.hh:244
static const int LcdTiming3
Definition pl111.hh:70
uint32_t clcdCrsrPalette1
Definition pl111.hh:241
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition pl111.cc:741
Pl111(const Params &p)
Definition pl111.cc:60
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
Definition pl111.hh:259
uint32_t clcdCrsrPalette0
Cursor palette registers.
Definition pl111.hh:240
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition pl111.cc:525
FrameBuffer fb
Definition pl111.hh:265
static const int LcdControl
Definition pl111.hh:73
TimingReg2 lcdTiming2
Clock and signal polarity control register.
Definition pl111.hh:202
TimingReg1 lcdTiming1
Vertical axis panel control register.
Definition pl111.hh:199
Addr maxAddr
Frame buffer max address.
Definition pl111.hh:295
static const int LcdRis
Definition pl111.hh:75
static const int LcdLpBase
Definition pl111.hh:72
static const int LcdMaxHeight
Definition pl111.hh:97
bool enableCapture
Definition pl111.hh:361
Pl111Params Params
Definition pl111.hh:364
static const int LcdPaletteSize
Definition pl111.hh:93
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
Definition pl111.hh:286
static const int ClcdCrsrConfig
Definition pl111.hh:83
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
Definition pl111.hh:256
Tick startTime
Start time for frame buffer dma read.
Definition pl111.hh:289
uint32_t lcdUpbase
Upper panel frame base address register.
Definition pl111.hh:208
PixelConverter converter
Definition pl111.hh:264
static const int maxOutstandingDma
Definition pl111.hh:100
InterruptReg lcdImsc
Interrupt mask set/clear register.
Definition pl111.hh:217
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:215
uint16_t width
Frame buffer width - pixels per line.
Definition pl111.hh:277
static const int ClcdCrsrMis
Definition pl111.hh:91
uint8_t bytesPerPixel
Bytes per pixel.
Definition pl111.hh:283
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
Definition pl111.hh:352
static const int LcdImsc
Definition pl111.hh:74
static const int LcdUpBase
Definition pl111.hh:71
static const int LcdMis
Definition pl111.hh:76
static const int LcdTiming2
Definition pl111.hh:69
uint16_t height
Frame buffer height - lines per panel.
Definition pl111.hh:280
static const int dmaSize
Definition pl111.hh:99
EventFunctionWrapper fillFifoEvent
Fill fifo.
Definition pl111.hh:333
TimingReg3 lcdTiming3
Line end control register.
Definition pl111.hh:205
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
Definition pl111.hh:355
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
Definition pl111.hh:231
uint32_t clcdCrsrCtrl
Cursor control register.
Definition pl111.hh:234
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
Definition pl111.hh:250
InterruptReg lcdMis
Masked interrupt status register.
Definition pl111.hh:223
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Definition pl111.hh:253
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
Definition pl111.hh:227
static const int LcdUpCurr
Definition pl111.hh:78
uint32_t lcdLpbase
Lower panel frame base address register.
Definition pl111.hh:211
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:100
static const int ClcdCrsrRis
Definition pl111.hh:90
static const int CrsrImage
Definition pl111.hh:81
void readFramebuffer()
DMA framebuffer read.
Definition pl111.cc:427
Tick pixelClock
Pixel clock.
Definition pl111.hh:262
static const int ClcdCrsrPalette1
Definition pl111.hh:85
uint32_t clcdCrsrConfig
Cursor configuration register.
Definition pl111.hh:237
static const int LcdTiming0
ARM PL111 register map.
Definition pl111.hh:67
VncInput * vnc
VNC server.
Definition pl111.hh:268
static const int LcdTiming1
Definition pl111.hh:68
PixelConverter pixelConverter() const
Definition pl111.cc:357
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Definition pl111.hh:359
static const int CrsrImageSize
Definition pl111.hh:94
uint32_t waterMark
DMA FIFO watermark.
Definition pl111.hh:301
static const int LcdPalette
Definition pl111.hh:80
static const int buffer_size
Definition pl111.hh:102
uint32_t dmaPendingNum
Number of pending dma reads.
Definition pl111.hh:304
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition pl111.cc:615
void generateInterrupt()
Function to generate interrupt.
Definition pl111.cc:728
void startDma()
start the dmas off after power is enabled
Definition pl111.cc:419
static const int ClcdCrsrIcr
Definition pl111.hh:89
BmpWriter bmp
Helper to write out bitmaps.
Definition pl111.hh:271
void fillFifo()
fillFIFO event
Definition pl111.cc:450
static const int ClcdCrsrImsc
Definition pl111.hh:88
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
Definition pl111.hh:168
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition pl111.hh:274
InterruptReg lcdRis
Raw interrupt status register - const.
Definition pl111.hh:220
static const int LcdIcr
Definition pl111.hh:77
static const uint64_t AMBA_ID
Definition pl111.hh:65
static const int ClcdCrsrPalette0
Definition pl111.hh:84
static const int ClcdCrsrClip
Definition pl111.hh:87
void updateVideoParams()
Send updated parameters to the vnc server.
Definition pl111.cc:399
@ UNCACHEABLE
The request is to an uncacheable address.
Definition request.hh:125
STL vector class.
Definition stl.hh:37
AddrRange RangeSize(Addr start, Addr size)
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition addr_range.hh:64
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:220
#define UNSERIALIZE_CONTAINER(member)
Definition serialize.hh:651
#define UNSERIALIZE_ARRAY(member, size)
Definition serialize.hh:618
#define SERIALIZE_ARRAY(member, size)
Definition serialize.hh:610
#define SERIALIZE_CONTAINER(member)
Definition serialize.hh:643
#define warn(...)
Definition logging.hh:288
#define warn_once(...)
Definition logging.hh:292
Bitfield< 31 > rw
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 9 > fb
Bitfield< 10, 5 > event
Bitfield< 30, 0 > index
Bitfield< 0 > p
Bitfield< 3 > x
Definition pagetable.hh:78
Bitfield< 15, 8 > vector
Definition intmessage.hh:48
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
OutputDirectory simout
Definition output.cc:62
uint64_t Tick
Tick count type.
Definition types.hh:58
Packet * PacketPtr
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
Declaration of the Packet class.
Implementiation of a PL111 CLCD controller.
#define UNSERIALIZE_SCALAR(scalar)
Definition serialize.hh:575
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568
const std::string & name()
Definition trace.cc:48
Declaration of a VNC input.

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