gem5 [DEVELOP-FOR-25.0]
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pl111.cc
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1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "dev/arm/pl111.hh"
39
40#include "base/output.hh"
41#include "base/trace.hh"
42#include "base/vnc/vncinput.hh"
43#include "debug/PL111.hh"
44#include "debug/Uart.hh"
46#include "dev/arm/base_gic.hh"
47#include "mem/packet.hh"
48#include "mem/packet_access.hh"
49#include "sim/system.hh"
50
51// clang complains about std::set being overloaded with Packet::set if
52// we open up the entire namespace std
53using std::vector;
54
55namespace gem5
56{
57
58// initialize clcd registers
60 : AmbaDmaDevice(p, 0x10000), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
62 lcdRis(0), lcdMis(0),
66 pixelClock(p.pixel_clock),
68 vnc(p.vnc), bmp(&fb), pic(NULL),
72 readEvent([this]{ readFramebuffer(); }, name()),
73 fillFifoEvent([this]{ fillFifo(); }, name()),
74 dmaDoneEventAll(maxOutstandingDma, this),
75 dmaDoneEventFree(maxOutstandingDma),
76 intEvent([this]{ generateInterrupt(); }, name()),
77 enableCapture(p.enable_capture)
78{
79 dmaBuffer = new uint8_t[buffer_size];
80
81 memset(lcdPalette, 0, sizeof(lcdPalette));
82 memset(cursorImage, 0, sizeof(cursorImage));
83 memset(dmaBuffer, 0, buffer_size);
84
85 for (int i = 0; i < maxOutstandingDma; ++i)
86 dmaDoneEventFree[i] = &dmaDoneEventAll[i];
87
88 if (vnc)
89 vnc->setFrameBuffer(&fb);
90}
91
93{
94 delete[] dmaBuffer;
95}
96
97// read registers and frame buffer
98Tick
100{
101 // use a temporary data since the LCD registers are read/written with
102 // different size operations
103
104 uint32_t data = 0;
105
106 assert(pkt->getAddr() >= pioAddr &&
107 pkt->getAddr() < pioAddr + pioSize);
108
109 Addr daddr = pkt->getAddr() - pioAddr;
110
111 DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize());
112
113 switch (daddr) {
114 case LcdTiming0:
116 break;
117 case LcdTiming1:
119 break;
120 case LcdTiming2:
122 break;
123 case LcdTiming3:
125 break;
126 case LcdUpBase:
127 data = lcdUpbase;
128 break;
129 case LcdLpBase:
130 data = lcdLpbase;
131 break;
132 case LcdControl:
134 break;
135 case LcdImsc:
136 data = lcdImsc;
137 break;
138 case LcdRis:
139 data = lcdRis;
140 break;
141 case LcdMis:
142 data = lcdMis;
143 break;
144 case LcdIcr:
145 panic("LCD register at offset %#x is Write-Only\n", daddr);
146 break;
147 case LcdUpCurr:
148 data = curAddr;
149 break;
150 case LcdLpCurr:
151 data = curAddr;
152 break;
153 case ClcdCrsrCtrl:
155 break;
156 case ClcdCrsrConfig:
158 break;
159 case ClcdCrsrPalette0:
161 break;
162 case ClcdCrsrPalette1:
164 break;
165 case ClcdCrsrXY:
167 break;
168 case ClcdCrsrClip:
170 break;
171 case ClcdCrsrImsc:
173 break;
174 case ClcdCrsrIcr:
175 panic("CLCD register at offset %#x is Write-Only\n", daddr);
176 break;
177 case ClcdCrsrRis:
179 break;
180 case ClcdCrsrMis:
182 break;
183 default:
184 if (readId(pkt, AMBA_ID, pioAddr)) {
185 // Hack for variable size accesses
186 data = pkt->getUintX(ByteOrder::little);
187 break;
188 } else if (daddr >= CrsrImage && daddr <= 0xBFC) {
189 // CURSOR IMAGE
190 int index;
191 index = (daddr - CrsrImage) >> 2;
193 break;
194 } else if (daddr >= LcdPalette && daddr <= 0x3FC) {
195 // LCD Palette
196 int index;
197 index = (daddr - LcdPalette) >> 2;
199 break;
200 } else {
201 panic("Tried to read CLCD register at offset %#x that "
202 "doesn't exist\n", daddr);
203 break;
204 }
205 }
206
207 pkt->setUintX(data, ByteOrder::little);
208 pkt->makeAtomicResponse();
209 return pioDelay;
210}
211
212// write registers and frame buffer
213Tick
215{
216 // use a temporary data since the LCD registers are read/written with
217 // different size operations
218 //
219 const uint32_t data = pkt->getUintX(ByteOrder::little);
220
221 assert(pkt->getAddr() >= pioAddr &&
222 pkt->getAddr() < pioAddr + pioSize);
223
224 Addr daddr = pkt->getAddr() - pioAddr;
225
226 DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr,
227 pkt->getLE<uint8_t>(), pkt->getSize());
228
229 switch (daddr) {
230 case LcdTiming0:
232 // width = 16 * (PPL+1)
233 width = (lcdTiming0.ppl + 1) << 4;
234 break;
235 case LcdTiming1:
237 // height = LPP + 1
238 height = (lcdTiming1.lpp) + 1;
239 break;
240 case LcdTiming2:
242 break;
243 case LcdTiming3:
245 break;
246 case LcdUpBase:
247 lcdUpbase = data;
248 DPRINTF(PL111, "####### Upper panel base set to: %#x #######\n", lcdUpbase);
249 break;
250 case LcdLpBase:
251 warn_once("LCD dual screen mode not supported\n");
252 lcdLpbase = data;
253 DPRINTF(PL111, "###### Lower panel base set to: %#x #######\n", lcdLpbase);
254 break;
255 case LcdControl:
256 int old_lcdpwr;
257 old_lcdpwr = lcdControl.lcdpwr;
259
260 DPRINTF(PL111, "LCD power is:%d\n", lcdControl.lcdpwr);
261
262 // LCD power enable
263 if (lcdControl.lcdpwr && !old_lcdpwr) {
265 DPRINTF(PL111, " lcd size: height %d width %d\n", height, width);
266 waterMark = lcdControl.watermark ? 8 : 4;
267 startDma();
268 }
269 break;
270 case LcdImsc:
271 lcdImsc = data;
272 if (lcdImsc.vcomp)
273 panic("Interrupting on vcomp not supported\n");
274
276
277 if (!lcdMis)
278 interrupt->clear();
279
280 break;
281 case LcdRis:
282 panic("LCD register at offset %#x is Read-Only\n", daddr);
283 break;
284 case LcdMis:
285 panic("LCD register at offset %#x is Read-Only\n", daddr);
286 break;
287 case LcdIcr:
288 lcdRis = lcdRis & ~data;
290
291 if (!lcdMis)
292 interrupt->clear();
293
294 break;
295 case LcdUpCurr:
296 panic("LCD register at offset %#x is Read-Only\n", daddr);
297 break;
298 case LcdLpCurr:
299 panic("LCD register at offset %#x is Read-Only\n", daddr);
300 break;
301 case ClcdCrsrCtrl:
303 break;
304 case ClcdCrsrConfig:
306 break;
307 case ClcdCrsrPalette0:
309 break;
310 case ClcdCrsrPalette1:
312 break;
313 case ClcdCrsrXY:
315 break;
316 case ClcdCrsrClip:
318 break;
319 case ClcdCrsrImsc:
321 break;
322 case ClcdCrsrIcr:
324 break;
325 case ClcdCrsrRis:
326 panic("CLCD register at offset %#x is Read-Only\n", daddr);
327 break;
328 case ClcdCrsrMis:
329 panic("CLCD register at offset %#x is Read-Only\n", daddr);
330 break;
331 default:
332 if (daddr >= CrsrImage && daddr <= 0xBFC) {
333 // CURSOR IMAGE
334 int index;
335 index = (daddr - CrsrImage) >> 2;
337 break;
338 } else if (daddr >= LcdPalette && daddr <= 0x3FC) {
339 // LCD Palette
340 int index;
341 index = (daddr - LcdPalette) >> 2;
343 break;
344 } else {
345 panic("Tried to write PL111 register at offset %#x that "
346 "doesn't exist\n", daddr);
347 break;
348 }
349 }
350
351 pkt->makeAtomicResponse();
352 return pioDelay;
353}
354
357{
358 unsigned rw, gw, bw;
359 unsigned offsets[3];
360
361 switch (lcdControl.lcdbpp) {
362 case bpp24:
363 rw = gw = bw = 8;
364 offsets[0] = 0;
365 offsets[1] = 8;
366 offsets[2] = 16;
367 break;
368
369 case bpp16m565:
370 rw = 5;
371 gw = 6;
372 bw = 5;
373 offsets[0] = 0;
374 offsets[1] = 5;
375 offsets[2] = 11;
376 break;
377
378 default:
379 panic("Unimplemented video mode\n");
380 }
381
382 if (lcdControl.bgr) {
383 return PixelConverter(
385 offsets[2], offsets[1], offsets[0],
386 rw, gw, bw,
387 ByteOrder::little);
388 } else {
389 return PixelConverter(
391 offsets[0], offsets[1], offsets[2],
392 rw, gw, bw,
393 ByteOrder::little);
394 }
395}
396
397void
399{
400 if (lcdControl.lcdbpp == bpp24) {
401 bytesPerPixel = 4;
402 } else if (lcdControl.lcdbpp == bpp16m565) {
403 bytesPerPixel = 2;
404 }
405
406 fb.resize(width, height);
408
409 // Workaround configuration bugs where multiple display
410 // controllers are attached to the same VNC server by reattaching
411 // enabled devices. This isn't ideal, but works as long as only
412 // one display controller is active at a time.
413 if (lcdControl.lcdpwr && vnc)
414 vnc->setFrameBuffer(&fb);
415}
416
417void
419{
420 if (dmaPendingNum != 0 || readEvent.scheduled())
421 return;
423}
424
425void
427{
428 // initialization for dma read from frame buffer to dma buffer
429 uint32_t length = height * width;
430 if (startAddr != lcdUpbase)
432
433 // Updating base address, interrupt if we're supposed to
434 lcdRis.baseaddr = 1;
435 if (!intEvent.scheduled())
437
438 curAddr = 0;
439 startTime = curTick();
440
441 maxAddr = static_cast<Addr>(length * bytesPerPixel);
442
443 DPRINTF(PL111, " lcd frame buffer size of %d bytes \n", maxAddr);
444
445 fillFifo();
446}
447
448void
450{
451 while ((dmaPendingNum < maxOutstandingDma) && (maxAddr >= curAddr + dmaSize )) {
452 // concurrent dma reads need different dma done events
453 // due to assertion in scheduling state
455
456 assert(!dmaDoneEventFree.empty());
457 DmaDoneEvent *event(dmaDoneEventFree.back());
458 dmaDoneEventFree.pop_back();
459 assert(!event->scheduled());
460
461 // We use a uncachable request here because the requests from the CPU
462 // will be uncacheable as well. If we have uncacheable and cacheable
463 // requests in the memory system for the same address it won't be
464 // pleased
468 curAddr += dmaSize;
469 }
470}
471
472void
474{
475 DPRINTF(PL111, "DMA Done\n");
476
477 Tick maxFrameTime = lcdTiming2.cpl * height * pixelClock;
478
480
481 if (maxAddr == curAddr && !dmaPendingNum) {
482 if ((curTick() - startTime) > maxFrameTime) {
483 warn("CLCD controller buffer underrun, took %d ticks when should"
484 " have taken %d\n", curTick() - startTime, maxFrameTime);
485 lcdRis.underflow = 1;
486 if (!intEvent.scheduled())
488 }
489
490 assert(!readEvent.scheduled());
491 fb.copyIn(dmaBuffer, converter);
492 if (vnc)
493 vnc->setDirty();
494
495 if (enableCapture) {
496 DPRINTF(PL111, "-- write out frame buffer into bmp\n");
497
498 if (!pic)
499 pic = simout.create(csprintf("%s.framebuffer.bmp", sys->name()),
500 true);
501
502 assert(pic);
503 pic->stream()->seekp(0);
504 bmp.write(*pic->stream());
505 }
506
507 // schedule the next read based on when the last frame started
508 // and the desired fps (i.e. maxFrameTime), we turn the
509 // argument into a relative number of cycles in the future
510 if (lcdControl.lcden)
512 curTick() +
513 maxFrameTime)));
514 }
515
517 return;
518
519 if (!fillFifoEvent.scheduled())
521}
522
523void
525{
526 DPRINTF(PL111, "Serializing ARM PL111\n");
527
528 uint32_t lcdTiming0_serial = lcdTiming0;
529 SERIALIZE_SCALAR(lcdTiming0_serial);
530
531 uint32_t lcdTiming1_serial = lcdTiming1;
532 SERIALIZE_SCALAR(lcdTiming1_serial);
533
534 uint32_t lcdTiming2_serial = lcdTiming2;
535 SERIALIZE_SCALAR(lcdTiming2_serial);
536
537 uint32_t lcdTiming3_serial = lcdTiming3;
538 SERIALIZE_SCALAR(lcdTiming3_serial);
539
542
543 uint32_t lcdControl_serial = lcdControl;
544 SERIALIZE_SCALAR(lcdControl_serial);
545
546 uint8_t lcdImsc_serial = lcdImsc;
547 SERIALIZE_SCALAR(lcdImsc_serial);
548
549 uint8_t lcdRis_serial = lcdRis;
550 SERIALIZE_SCALAR(lcdRis_serial);
551
552 uint8_t lcdMis_serial = lcdMis;
553 SERIALIZE_SCALAR(lcdMis_serial);
554
557
564
565 uint8_t clcdCrsrImsc_serial = clcdCrsrImsc;
566 SERIALIZE_SCALAR(clcdCrsrImsc_serial);
567
568 uint8_t clcdCrsrIcr_serial = clcdCrsrIcr;
569 SERIALIZE_SCALAR(clcdCrsrIcr_serial);
570
571 uint8_t clcdCrsrRis_serial = clcdCrsrRis;
572 SERIALIZE_SCALAR(clcdCrsrRis_serial);
573
574 uint8_t clcdCrsrMis_serial = clcdCrsrMis;
575 SERIALIZE_SCALAR(clcdCrsrMis_serial);
576
580
588
589 Tick int_event_time = 0;
590 Tick read_event_time = 0;
591 Tick fill_fifo_event_time = 0;
592
593 if (readEvent.scheduled())
594 read_event_time = readEvent.when();
595 if (fillFifoEvent.scheduled())
596 fill_fifo_event_time = fillFifoEvent.when();
597 if (intEvent.scheduled())
598 int_event_time = intEvent.when();
599
600 SERIALIZE_SCALAR(read_event_time);
601 SERIALIZE_SCALAR(fill_fifo_event_time);
602 SERIALIZE_SCALAR(int_event_time);
603
604 vector<Tick> dma_done_event_tick;
605 dma_done_event_tick.resize(maxOutstandingDma);
606 for (int x = 0; x < maxOutstandingDma; x++) {
607 dma_done_event_tick[x] = dmaDoneEventAll[x].scheduled() ?
608 dmaDoneEventAll[x].when() : 0;
609 }
610 SERIALIZE_CONTAINER(dma_done_event_tick);
611}
612
613void
615{
616 DPRINTF(PL111, "Unserializing ARM PL111\n");
617
618 uint32_t lcdTiming0_serial;
619 UNSERIALIZE_SCALAR(lcdTiming0_serial);
620 lcdTiming0 = lcdTiming0_serial;
621
622 uint32_t lcdTiming1_serial;
623 UNSERIALIZE_SCALAR(lcdTiming1_serial);
624 lcdTiming1 = lcdTiming1_serial;
625
626 uint32_t lcdTiming2_serial;
627 UNSERIALIZE_SCALAR(lcdTiming2_serial);
628 lcdTiming2 = lcdTiming2_serial;
629
630 uint32_t lcdTiming3_serial;
631 UNSERIALIZE_SCALAR(lcdTiming3_serial);
632 lcdTiming3 = lcdTiming3_serial;
633
636
637 uint32_t lcdControl_serial;
638 UNSERIALIZE_SCALAR(lcdControl_serial);
639 lcdControl = lcdControl_serial;
640
641 uint8_t lcdImsc_serial;
642 UNSERIALIZE_SCALAR(lcdImsc_serial);
643 lcdImsc = lcdImsc_serial;
644
645 uint8_t lcdRis_serial;
646 UNSERIALIZE_SCALAR(lcdRis_serial);
647 lcdRis = lcdRis_serial;
648
649 uint8_t lcdMis_serial;
650 UNSERIALIZE_SCALAR(lcdMis_serial);
651 lcdMis = lcdMis_serial;
652
655
662
663 uint8_t clcdCrsrImsc_serial;
664 UNSERIALIZE_SCALAR(clcdCrsrImsc_serial);
665 clcdCrsrImsc = clcdCrsrImsc_serial;
666
667 uint8_t clcdCrsrIcr_serial;
668 UNSERIALIZE_SCALAR(clcdCrsrIcr_serial);
669 clcdCrsrIcr = clcdCrsrIcr_serial;
670
671 uint8_t clcdCrsrRis_serial;
672 UNSERIALIZE_SCALAR(clcdCrsrRis_serial);
673 clcdCrsrRis = clcdCrsrRis_serial;
674
675 uint8_t clcdCrsrMis_serial;
676 UNSERIALIZE_SCALAR(clcdCrsrMis_serial);
677 clcdCrsrMis = clcdCrsrMis_serial;
678
682
690
691 Tick int_event_time = 0;
692 Tick read_event_time = 0;
693 Tick fill_fifo_event_time = 0;
694
695 UNSERIALIZE_SCALAR(read_event_time);
696 UNSERIALIZE_SCALAR(fill_fifo_event_time);
697 UNSERIALIZE_SCALAR(int_event_time);
698
699 if (int_event_time)
700 schedule(intEvent, int_event_time);
701 if (read_event_time)
702 schedule(readEvent, read_event_time);
703 if (fill_fifo_event_time)
704 schedule(fillFifoEvent, fill_fifo_event_time);
705
706 vector<Tick> dma_done_event_tick;
707 dma_done_event_tick.resize(maxOutstandingDma);
708 UNSERIALIZE_CONTAINER(dma_done_event_tick);
709 dmaDoneEventFree.clear();
710 for (int x = 0; x < maxOutstandingDma; x++) {
711 if (dma_done_event_tick[x])
712 schedule(dmaDoneEventAll[x], dma_done_event_tick[x]);
713 else
715 }
717
718 if (lcdControl.lcdpwr) {
720 fb.copyIn(dmaBuffer, converter);
721 if (vnc)
722 vnc->setDirty();
723 }
724}
725
726void
728{
729 DPRINTF(PL111, "Generate Interrupt: lcdImsc=0x%x lcdRis=0x%x lcdMis=0x%x\n",
730 (uint32_t)lcdImsc, (uint32_t)lcdRis, (uint32_t)lcdMis);
732
733 if (lcdMis.underflow || lcdMis.baseaddr || lcdMis.vcomp || lcdMis.ahbmaster) {
734 interrupt->raise();
735 DPRINTF(PL111, " -- Generated\n");
736 }
737}
738
741{
742 AddrRangeList ranges;
743 ranges.push_back(RangeSize(pioAddr, pioSize));
744 return ranges;
745}
746
747} // namespace gem5
This is a base class for AMBA devices that have to respond to Device and Implementer ID calls.
#define DPRINTF(x,...)
Definition trace.hh:209
Base class for ARM GIC implementations.
const char data[]
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
ArmInterruptPin *const interrupt
AmbaDmaDevice(const Params &p, Addr pio_size=0)
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles ticksToCycles(Tick t) const
Addr getAddr() const
Definition packet.hh:807
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition packet.cc:361
unsigned getSize() const
Definition packet.hh:817
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition packet.cc:352
void makeAtomicResponse()
Definition packet.hh:1074
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Configurable RGB pixel converter.
Definition pixel.hh:92
void dmaDone()
DMA done event.
Definition pl111.cc:473
static const int LcdLpCurr
Definition pl111.hh:78
static const int ClcdCrsrCtrl
Definition pl111.hh:81
Addr curAddr
Frame buffer current address.
Definition pl111.hh:297
EventFunctionWrapper readEvent
DMA framebuffer read event.
Definition pl111.hh:329
static const int ClcdCrsrXY
Definition pl111.hh:85
uint32_t clcdCrsrClip
Cursor clip position register.
Definition pl111.hh:246
Addr startAddr
Frame buffer base address.
Definition pl111.hh:291
ControlReg lcdControl
Control register.
Definition pl111.hh:213
static const int LcdMaxWidth
Definition pl111.hh:95
uint32_t clcdCrsrXY
Cursor XY position register.
Definition pl111.hh:243
static const int LcdTiming3
Definition pl111.hh:69
uint32_t clcdCrsrPalette1
Definition pl111.hh:240
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition pl111.cc:740
Pl111(const Params &p)
Definition pl111.cc:59
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
Definition pl111.hh:258
uint32_t clcdCrsrPalette0
Cursor palette registers.
Definition pl111.hh:239
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition pl111.cc:524
FrameBuffer fb
Definition pl111.hh:264
static const int LcdControl
Definition pl111.hh:72
TimingReg2 lcdTiming2
Clock and signal polarity control register.
Definition pl111.hh:201
TimingReg1 lcdTiming1
Vertical axis panel control register.
Definition pl111.hh:198
Addr maxAddr
Frame buffer max address.
Definition pl111.hh:294
static const int LcdRis
Definition pl111.hh:74
static const int LcdLpBase
Definition pl111.hh:71
static const int LcdMaxHeight
Definition pl111.hh:96
bool enableCapture
Definition pl111.hh:360
Pl111Params Params
Definition pl111.hh:363
static const int LcdPaletteSize
Definition pl111.hh:92
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
Definition pl111.hh:285
static const int ClcdCrsrConfig
Definition pl111.hh:82
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
Definition pl111.hh:255
Tick startTime
Start time for frame buffer dma read.
Definition pl111.hh:288
uint32_t lcdUpbase
Upper panel frame base address register.
Definition pl111.hh:207
PixelConverter converter
Definition pl111.hh:263
static const int maxOutstandingDma
Definition pl111.hh:99
InterruptReg lcdImsc
Interrupt mask set/clear register.
Definition pl111.hh:216
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:214
uint16_t width
Frame buffer width - pixels per line.
Definition pl111.hh:276
static const int ClcdCrsrMis
Definition pl111.hh:90
uint8_t bytesPerPixel
Bytes per pixel.
Definition pl111.hh:282
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
Definition pl111.hh:351
static const int LcdImsc
Definition pl111.hh:73
static const int LcdUpBase
Definition pl111.hh:70
static const int LcdMis
Definition pl111.hh:75
static const int LcdTiming2
Definition pl111.hh:68
uint16_t height
Frame buffer height - lines per panel.
Definition pl111.hh:279
static const int dmaSize
Definition pl111.hh:98
EventFunctionWrapper fillFifoEvent
Fill fifo.
Definition pl111.hh:332
TimingReg3 lcdTiming3
Line end control register.
Definition pl111.hh:204
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
Definition pl111.hh:354
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
Definition pl111.hh:230
uint32_t clcdCrsrCtrl
Cursor control register.
Definition pl111.hh:233
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
Definition pl111.hh:249
InterruptReg lcdMis
Masked interrupt status register.
Definition pl111.hh:222
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Definition pl111.hh:252
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
Definition pl111.hh:226
static const int LcdUpCurr
Definition pl111.hh:77
uint32_t lcdLpbase
Lower panel frame base address register.
Definition pl111.hh:210
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:99
static const int ClcdCrsrRis
Definition pl111.hh:89
static const int CrsrImage
Definition pl111.hh:80
void readFramebuffer()
DMA framebuffer read.
Definition pl111.cc:426
Tick pixelClock
Pixel clock.
Definition pl111.hh:261
static const int ClcdCrsrPalette1
Definition pl111.hh:84
uint32_t clcdCrsrConfig
Cursor configuration register.
Definition pl111.hh:236
static const int LcdTiming0
ARM PL111 register map.
Definition pl111.hh:66
VncInput * vnc
VNC server.
Definition pl111.hh:267
static const int LcdTiming1
Definition pl111.hh:67
PixelConverter pixelConverter() const
Definition pl111.cc:356
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Definition pl111.hh:358
static const int CrsrImageSize
Definition pl111.hh:93
uint32_t waterMark
DMA FIFO watermark.
Definition pl111.hh:300
static const int LcdPalette
Definition pl111.hh:79
static const int buffer_size
Definition pl111.hh:101
uint32_t dmaPendingNum
Number of pending dma reads.
Definition pl111.hh:303
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition pl111.cc:614
void generateInterrupt()
Function to generate interrupt.
Definition pl111.cc:727
void startDma()
start the dmas off after power is enabled
Definition pl111.cc:418
static const int ClcdCrsrIcr
Definition pl111.hh:88
BmpWriter bmp
Helper to write out bitmaps.
Definition pl111.hh:270
void fillFifo()
fillFIFO event
Definition pl111.cc:449
static const int ClcdCrsrImsc
Definition pl111.hh:87
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
Definition pl111.hh:167
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition pl111.hh:273
InterruptReg lcdRis
Raw interrupt status register - const.
Definition pl111.hh:219
static const int LcdIcr
Definition pl111.hh:76
static const uint64_t AMBA_ID
Definition pl111.hh:64
static const int ClcdCrsrPalette0
Definition pl111.hh:83
static const int ClcdCrsrClip
Definition pl111.hh:86
void updateVideoParams()
Send updated parameters to the vnc server.
Definition pl111.cc:398
@ UNCACHEABLE
The request is to an uncacheable address.
Definition request.hh:125
STL vector class.
Definition stl.hh:37
AddrRange RangeSize(Addr start, Addr size)
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition addr_range.hh:64
void schedule(Event &event, Tick when)
Definition eventq.hh:1012
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:220
#define UNSERIALIZE_CONTAINER(member)
Definition serialize.hh:651
#define UNSERIALIZE_ARRAY(member, size)
Definition serialize.hh:618
#define SERIALIZE_ARRAY(member, size)
Definition serialize.hh:610
#define SERIALIZE_CONTAINER(member)
Definition serialize.hh:643
#define warn(...)
Definition logging.hh:288
#define warn_once(...)
Definition logging.hh:292
Bitfield< 31 > rw
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 9 > fb
Bitfield< 10, 5 > event
Bitfield< 30, 0 > index
Bitfield< 0 > p
Bitfield< 3 > x
Definition pagetable.hh:76
Bitfield< 15, 8 > vector
Definition intmessage.hh:48
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
OutputDirectory simout
Definition output.cc:62
uint64_t Tick
Tick count type.
Definition types.hh:58
Packet * PacketPtr
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
Declaration of the Packet class.
Implementiation of a PL111 CLCD controller.
#define UNSERIALIZE_SCALAR(scalar)
Definition serialize.hh:575
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568
const std::string & name()
Definition trace.cc:48
Declaration of a VNC input.

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