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pl111.hh
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1/*
2 * Copyright (c) 2010-2012, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38
42
43#ifndef __DEV_ARM_PL111_HH__
44#define __DEV_ARM_PL111_HH__
45
46#include <fstream>
47#include <memory>
48
49#include "base/bmpwriter.hh"
50#include "base/framebuffer.hh"
51#include "base/output.hh"
53#include "sim/serialize.hh"
54
55namespace gem5
56{
57
58class VncInput;
59
60struct Pl111Params;
61
62class Pl111: public AmbaDmaDevice
63{
64 protected:
65 static const uint64_t AMBA_ID = 0xb105f00d00141111ULL;
67 static const int LcdTiming0 = 0x000;
68 static const int LcdTiming1 = 0x004;
69 static const int LcdTiming2 = 0x008;
70 static const int LcdTiming3 = 0x00C;
71 static const int LcdUpBase = 0x010;
72 static const int LcdLpBase = 0x014;
73 static const int LcdControl = 0x018;
74 static const int LcdImsc = 0x01C;
75 static const int LcdRis = 0x020;
76 static const int LcdMis = 0x024;
77 static const int LcdIcr = 0x028;
78 static const int LcdUpCurr = 0x02C;
79 static const int LcdLpCurr = 0x030;
80 static const int LcdPalette = 0x200;
81 static const int CrsrImage = 0x800;
82 static const int ClcdCrsrCtrl = 0xC00;
83 static const int ClcdCrsrConfig = 0xC04;
84 static const int ClcdCrsrPalette0 = 0xC08;
85 static const int ClcdCrsrPalette1 = 0xC0C;
86 static const int ClcdCrsrXY = 0xC10;
87 static const int ClcdCrsrClip = 0xC14;
88 static const int ClcdCrsrImsc = 0xC20;
89 static const int ClcdCrsrIcr = 0xC24;
90 static const int ClcdCrsrRis = 0xC28;
91 static const int ClcdCrsrMis = 0xC2C;
92
93 static const int LcdPaletteSize = 128;
94 static const int CrsrImageSize = 256;
95
96 static const int LcdMaxWidth = 1024; // pixels per line
97 static const int LcdMaxHeight = 768; // lines per panel
98
99 static const int dmaSize = 8; // 64 bits
100 static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits
101
102 static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
103
115
116 BitUnion8(InterruptReg)
117 Bitfield<1> underflow;
118 Bitfield<2> baseaddr;
119 Bitfield<3> vcomp;
120 Bitfield<4> ahbmaster;
121 EndBitUnion(InterruptReg)
122
123 BitUnion32(TimingReg0)
124 Bitfield<7,2> ppl;
125 Bitfield<15,8> hsw;
126 Bitfield<23,16> hfp;
127 Bitfield<31,24> hbp;
128 EndBitUnion(TimingReg0)
129
130 BitUnion32(TimingReg1)
131 Bitfield<9,0> lpp;
132 Bitfield<15,10> vsw;
133 Bitfield<23,16> vfp;
134 Bitfield<31,24> vbp;
135 EndBitUnion(TimingReg1)
136
137 BitUnion32(TimingReg2)
138 Bitfield<4,0> pcdlo;
139 Bitfield<5> clksel;
140 Bitfield<10,6> acb;
141 Bitfield<11> avs;
142 Bitfield<12> ihs;
143 Bitfield<13> ipc;
144 Bitfield<14> ioe;
145 Bitfield<25,16> cpl;
146 Bitfield<26> bcd;
147 Bitfield<31,27> pcdhi;
148 EndBitUnion(TimingReg2)
149
150 BitUnion32(TimingReg3)
151 Bitfield<6,0> led;
152 Bitfield<16> lee;
153 EndBitUnion(TimingReg3)
154
155 BitUnion32(ControlReg)
156 Bitfield<0> lcden;
157 Bitfield<3,1> lcdbpp;
158 Bitfield<4> lcdbw;
159 Bitfield<5> lcdtft;
160 Bitfield<6> lcdmono8;
161 Bitfield<7> lcddual;
162 Bitfield<8> bgr;
163 Bitfield<9> bebo;
164 Bitfield<10> bepo;
165 Bitfield<11> lcdpwr;
166 Bitfield<13,12> lcdvcomp;
167 Bitfield<16> watermark;
168 EndBitUnion(ControlReg)
169
176 class DmaDoneEvent : public Event
177 {
178 private:
179 Pl111 &obj;
180
181 public:
182 DmaDoneEvent(Pl111 *_obj)
183 : Event(), obj(*_obj) {}
184
185 void process() {
186 obj.dmaDoneEventFree.push_back(this);
187 obj.dmaDone();
188 }
189
190 const std::string name() const {
191 return obj.name() + ".DmaDoneEvent";
192 }
193 };
194
196 TimingReg0 lcdTiming0;
197
199 TimingReg1 lcdTiming1;
200
202 TimingReg2 lcdTiming2;
203
205 TimingReg3 lcdTiming3;
206
208 uint32_t lcdUpbase;
209
211 uint32_t lcdLpbase;
212
214 ControlReg lcdControl;
215
217 InterruptReg lcdImsc;
218
220 InterruptReg lcdRis;
221
223 InterruptReg lcdMis;
224
228
232
234 uint32_t clcdCrsrCtrl;
235
238
242
244 uint32_t clcdCrsrXY;
245
247 uint32_t clcdCrsrClip;
248
250 InterruptReg clcdCrsrImsc;
251
253 InterruptReg clcdCrsrIcr;
254
256 InterruptReg clcdCrsrRis;
257
259 InterruptReg clcdCrsrMis;
260
263
266
269
272
275
277 uint16_t width;
278
280 uint16_t height;
281
284
286 uint8_t *dmaBuffer;
287
290
293
296
299
301 uint32_t waterMark;
302
305
307
309 void updateVideoParams();
310
312 void readFramebuffer();
313
316
318 void generateInterrupt();
319
321 void fillFifo();
322
324 void startDma();
325
327 void dmaDone();
328
331
334
353
357
360
362
363 public:
364 using Params = Pl111Params;
365 Pl111(const Params &p);
366 ~Pl111();
367
368 Tick read(PacketPtr pkt) override;
369 Tick write(PacketPtr pkt) override;
370
371 void serialize(CheckpointOut &cp) const override;
372 void unserialize(CheckpointIn &cp) override;
373
379 AddrRangeList getAddrRanges() const override;
380};
381
382} // namespace gem5
383
384#endif
This is a base class for AMBA devices that have to respond to Device and Implementer ID calls.
#define BitUnion32(name)
Definition bitunion.hh:495
AmbaDmaDevice(const Params &p, Addr pio_size=0)
Internal gem5 representation of a frame buffer.
virtual std::string name() const
Definition named.hh:60
Configurable RGB pixel converter.
Definition pixel.hh:92
void dmaDone()
DMA done event.
Definition pl111.cc:474
Bitfield< 13, 12 > lcdvcomp
Definition pl111.hh:166
Bitfield< 3 > vcomp
Definition pl111.hh:119
Bitfield< 4 > lcdbw
Definition pl111.hh:158
static const int LcdLpCurr
Definition pl111.hh:79
static const int ClcdCrsrCtrl
Definition pl111.hh:82
Addr curAddr
Frame buffer current address.
Definition pl111.hh:298
Bitfield< 31, 24 > vbp
Definition pl111.hh:134
Bitfield< 3, 1 > lcdbpp
Definition pl111.hh:157
EventFunctionWrapper readEvent
DMA framebuffer read event.
Definition pl111.hh:330
static const int ClcdCrsrXY
Definition pl111.hh:86
uint32_t clcdCrsrClip
Cursor clip position register.
Definition pl111.hh:247
Bitfield< 31, 27 > pcdhi
Definition pl111.hh:147
Bitfield< 5 > lcdtft
Definition pl111.hh:159
Bitfield< 7 > lcddual
Definition pl111.hh:161
Addr startAddr
Frame buffer base address.
Definition pl111.hh:292
ControlReg lcdControl
Control register.
Definition pl111.hh:214
static const int LcdMaxWidth
Definition pl111.hh:96
Bitfield< 10 > bepo
Definition pl111.hh:164
Bitfield< 4 > ahbmaster
Definition pl111.hh:120
Bitfield< 2 > baseaddr
Definition pl111.hh:118
Bitfield< 8 > bgr
Definition pl111.hh:162
uint32_t clcdCrsrXY
Cursor XY position register.
Definition pl111.hh:244
static const int LcdTiming3
Definition pl111.hh:70
Bitfield< 6 > lcdmono8
Definition pl111.hh:160
uint32_t clcdCrsrPalette1
Definition pl111.hh:241
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition pl111.cc:741
Pl111(const Params &p)
Definition pl111.cc:60
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
Definition pl111.hh:259
uint32_t clcdCrsrPalette0
Cursor palette registers.
Definition pl111.hh:240
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition pl111.cc:525
EndBitUnion(InterruptReg) BitUnion32(TimingReg0) Bitfield< 7
FrameBuffer fb
Definition pl111.hh:265
static const int LcdControl
Definition pl111.hh:73
Bitfield< 31, 24 > hbp
Definition pl111.hh:127
TimingReg2 lcdTiming2
Clock and signal polarity control register.
Definition pl111.hh:202
TimingReg1 lcdTiming1
Vertical axis panel control register.
Definition pl111.hh:199
Addr maxAddr
Frame buffer max address.
Definition pl111.hh:295
static const int LcdRis
Definition pl111.hh:75
static const int LcdLpBase
Definition pl111.hh:72
static const int LcdMaxHeight
Definition pl111.hh:97
bool enableCapture
Definition pl111.hh:361
Pl111Params Params
Definition pl111.hh:364
static const int LcdPaletteSize
Definition pl111.hh:93
Bitfield< 23, 16 > hfp
Definition pl111.hh:126
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
Definition pl111.hh:286
static const int ClcdCrsrConfig
Definition pl111.hh:83
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
Definition pl111.hh:256
Bitfield< 23, 16 > vfp
Definition pl111.hh:133
Tick startTime
Start time for frame buffer dma read.
Definition pl111.hh:289
uint32_t lcdUpbase
Upper panel frame base address register.
Definition pl111.hh:208
PixelConverter converter
Definition pl111.hh:264
static const int maxOutstandingDma
Definition pl111.hh:100
InterruptReg lcdImsc
Interrupt mask set/clear register.
Definition pl111.hh:217
Bitfield< 13 > ipc
Definition pl111.hh:143
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:215
Bitfield< 9 > bebo
Definition pl111.hh:163
uint16_t width
Frame buffer width - pixels per line.
Definition pl111.hh:277
static const int ClcdCrsrMis
Definition pl111.hh:91
uint8_t bytesPerPixel
Bytes per pixel.
Definition pl111.hh:283
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
Definition pl111.hh:352
static const int LcdImsc
Definition pl111.hh:74
static const int LcdUpBase
Definition pl111.hh:71
void generateReadEvent()
Generate dma framebuffer read event.
static const int LcdMis
Definition pl111.hh:76
Bitfield< 16 > lee
Definition pl111.hh:152
static const int LcdTiming2
Definition pl111.hh:69
uint16_t height
Frame buffer height - lines per panel.
Definition pl111.hh:280
Bitfield< 11 > lcdpwr
Definition pl111.hh:165
static const int dmaSize
Definition pl111.hh:99
EventFunctionWrapper fillFifoEvent
Fill fifo.
Definition pl111.hh:333
TimingReg3 lcdTiming3
Line end control register.
Definition pl111.hh:205
Bitfield< 5 > clksel
Definition pl111.hh:139
Bitfield< 25, 16 > cpl
Definition pl111.hh:145
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
Definition pl111.hh:355
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
Definition pl111.hh:231
uint32_t clcdCrsrCtrl
Cursor control register.
Definition pl111.hh:234
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
Definition pl111.hh:250
Bitfield< 15, 8 > hsw
Definition pl111.hh:125
InterruptReg lcdMis
Masked interrupt status register.
Definition pl111.hh:223
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Definition pl111.hh:253
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
Definition pl111.hh:227
static const int LcdUpCurr
Definition pl111.hh:78
uint32_t lcdLpbase
Lower panel frame base address register.
Definition pl111.hh:211
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition pl111.cc:100
static const int ClcdCrsrRis
Definition pl111.hh:90
static const int CrsrImage
Definition pl111.hh:81
void readFramebuffer()
DMA framebuffer read.
Definition pl111.cc:427
Tick pixelClock
Pixel clock.
Definition pl111.hh:262
static const int ClcdCrsrPalette1
Definition pl111.hh:85
uint32_t clcdCrsrConfig
Cursor configuration register.
Definition pl111.hh:237
static const int LcdTiming0
ARM PL111 register map.
Definition pl111.hh:67
Bitfield< 14 > ioe
Definition pl111.hh:144
VncInput * vnc
VNC server.
Definition pl111.hh:268
Bitfield< 12 > ihs
Definition pl111.hh:142
static const int LcdTiming1
Definition pl111.hh:68
PixelConverter pixelConverter() const
Definition pl111.cc:357
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Definition pl111.hh:359
static const int CrsrImageSize
Definition pl111.hh:94
Bitfield< 10, 6 > acb
Definition pl111.hh:140
uint32_t waterMark
DMA FIFO watermark.
Definition pl111.hh:301
static const int LcdPalette
Definition pl111.hh:80
static const int buffer_size
Definition pl111.hh:102
uint32_t dmaPendingNum
Number of pending dma reads.
Definition pl111.hh:304
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition pl111.cc:615
void generateInterrupt()
Function to generate interrupt.
Definition pl111.cc:728
void startDma()
start the dmas off after power is enabled
Definition pl111.cc:419
Bitfield< 16 > watermark
Definition pl111.hh:167
static const int ClcdCrsrIcr
Definition pl111.hh:89
BmpWriter bmp
Helper to write out bitmaps.
Definition pl111.hh:271
void fillFifo()
fillFIFO event
Definition pl111.cc:450
static const int ClcdCrsrImsc
Definition pl111.hh:88
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
Definition pl111.hh:168
OutputStream * pic
Picture of what the current frame buffer looks like.
Definition pl111.hh:274
InterruptReg lcdRis
Raw interrupt status register - const.
Definition pl111.hh:220
Bitfield< 15, 10 > vsw
Definition pl111.hh:132
static const int LcdIcr
Definition pl111.hh:77
Bitfield< 26 > bcd
Definition pl111.hh:146
static const uint64_t AMBA_ID
Definition pl111.hh:65
static const int ClcdCrsrPalette0
Definition pl111.hh:84
static const int ClcdCrsrClip
Definition pl111.hh:87
Bitfield< 11 > avs
Definition pl111.hh:141
void updateVideoParams()
Send updated parameters to the vnc server.
Definition pl111.cc:399
BitUnion8(InterruptReg) Bitfield< 1 > underflow
STL vector class.
Definition stl.hh:37
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition addr_range.hh:64
BitUnion32(PackedIntReg) Bitfield< 31
Bitfield< 0 > p
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
Packet * PacketPtr
const std::string & name()
Definition trace.cc:48

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