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design.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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design.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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SC_MODULE
(design) {
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// ports
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sc_in_clk
clock;
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sc_in<bool >
take_the_data;
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sc_in<bool >
data_request;
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sc_out<bool >
data_ready;
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sc_out<bool >
write_in_is_done;
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sc_in <DATA_TYPE > input;
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sc_out<DATA_TYPE >
output;
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sc_signal<DATA_TYPE >
ring_buffer[
RING_BUFFER_SIZE
];
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sc_signal<INDEX_TYPE >
read_pointer;
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sc_signal<INDEX_TYPE >
write_pointer;
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// processes
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void
write_in_fifo();
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void
read_out_fifo();
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SC_CTOR
(design) {
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SC_CTHREAD
(write_in_fifo, clock.pos() );
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SC_CTHREAD
(read_out_fifo, clock.pos() );
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// bad reset
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write_pointer = (
INDEX_TYPE
)0 ;
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read_pointer = (
INDEX_TYPE
)0 ;
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}
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};
sc_in_clk
sc_in< bool > sc_in_clk
Definition
sc_clock.hh:116
sc_in
Definition
sc_in.hh:48
sc_out
Definition
sc_out.hh:39
sc_signal
Definition
sc_signal.hh:273
INDEX_TYPE
#define INDEX_TYPE
Definition
def.h:39
RING_BUFFER_SIZE
#define RING_BUFFER_SIZE
Definition
def.h:38
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition
sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition
sc_module.hh:295
SC_CTOR
#define SC_CTOR(name)
Definition
sc_module.hh:297
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