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systemc
tests
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misc
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test1.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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test1.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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SC_MODULE
(io_controller_m){
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/* ports */
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sc_in_clk
clk_i486_if;
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sc_out<sc_uint<30>
> addr30_o;
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sc_inout<sc_uint<32>
> data32_i;
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sc_out<sc_uint<32>
> data32_o;
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sc_out<bool>
ads_n_o;
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sc_out<bool>
wr_n_o;
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sc_in<bool>
rdy_n_i;
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sc_in<bool>
ar_i;
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sc_in<bool>
res_n_i;
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sc_out<sc_uint<4>
> mii_data4_o;
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sc_out<bool>
mii_en_o;
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sc_in<sc_uint<4>
> mii_data4_i;
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sc_in<bool>
mii_en_i;
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sc_in<bool>
mii_coll_det;
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sc_in_clk
clk_mii;
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/* signals */
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sc_signal<sc_uint<32>
> mux_data32;
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sc_signal<sc_uint<32>
> in_fifo_data32;
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sc_signal<sc_uint<32>
> out_fifo_data32;
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sc_signal<sc_uint<32>
> control_data32;
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sc_signal<bool>
out_fifo_en;
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sc_signal<bool>
out_fifo_act;
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sc_signal<bool>
in_fifo_en;
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sc_signal<bool>
control_en;
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sc_signal<bool>
out_fifo_reset;
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/* variables */
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sc_uint<32>
addr_tx_frame_ptr;
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sc_uint<32>
rx_ptr_array;
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sc_signal<bool>
value;
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SC_CTOR
(io_controller_m)
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{
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SC_CTHREAD
(control_write, clk_i486_if.pos());
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}
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void
control_write();
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};
sc_in_clk
sc_in< bool > sc_in_clk
Definition
sc_clock.hh:116
sc_in
Definition
sc_in.hh:48
sc_inout
Definition
sc_inout.hh:55
sc_out
Definition
sc_out.hh:39
sc_signal
Definition
sc_signal.hh:273
sc_uint
Definition
sc_uint.hh:87
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition
sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition
sc_module.hh:295
SC_CTOR
#define SC_CTOR(name)
Definition
sc_module.hh:297
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