29#ifndef __CPU_O3_STORE_SET_HH__
30#define __CPU_O3_STORE_SET_HH__
96 size_t SSIT_entries,
int SSIT_assoc,
104 void init(uint64_t clear_period,
105 size_t SSIT_entries,
int SSIT_assoc,
149 {
return ((PC ^ (PC >> 10)) %
LFSTSize); }
165 typedef std::map<InstSeqNum, int, ltseqnum>::iterator
SeqNumMapIt;
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
CacheEntry(TagExtractor ext)
Named(std::string_view name_)
std::function< Addr(Addr)> TagExtractor
SSITEntry(TagExtractor ext)
void insertLoad(Addr load_PC, InstSeqNum load_seq_num)
Inserts a load into the store set predictor.
void checkClear()
Clears the store set predictor every so often so that all the entries aren't used and stores are cons...
std::vector< InstSeqNum > LFST
Last Fetched Store Table.
void squash(InstSeqNum squashed_num, ThreadID tid)
Squashes for a specific thread until the given sequence number.
uint64_t clearPeriod
Number of loads/stores to process before wiping predictor so all entries don't get saturated.
void dump()
Debug function to dump the contents of the store list.
void clear()
Resets all tables.
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
Inserts a store into the store set predictor.
~StoreSet()
Default destructor.
SSID calcSSID(Addr PC)
Calculates a Store Set ID based on the PC.
std::vector< bool > validLFST
Bit vector to tell if the LFST has a valid entry.
int LFSTSize
Last Fetched Store Table size, in entries.
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
Records this PC/sequence number as issued.
InstSeqNum checkInst(Addr PC)
Checks if the instruction with the given PC is dependent upon any store.
AssociativeCache< SSITEntry > SSIT
The Store Set ID Table.
std::map< InstSeqNum, int, ltseqnum >::iterator SeqNumMapIt
int SSITSize
Store Set ID Table size, in entries.
StoreSet()
Default constructor.
void violation(Addr store_PC, Addr load_PC)
Records a memory ordering violation between the younger load and the older store.
std::map< InstSeqNum, int, ltseqnum > storeList
Map of stores that have been inserted into the store set, but not yet issued or squashed.
int memOpsPred
Number of memory operations predicted since last clear of predictor.
A common base class of cache replacement policy objects.
const FlagsType init
This Stat is Initialized.
Copyright (c) 2024 Arm Limited All rights reserved.
int16_t ThreadID
Thread index/ID type.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
IndexingPolicyTemplate< AddrTypes > BaseIndexingPolicy
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
const std::string & name()