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store_set.hh
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1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_STORE_SET_HH__
30#define __CPU_O3_STORE_SET_HH__
31
32#include <list>
33#include <map>
34#include <string_view>
35#include <utility>
36#include <vector>
37
40#include "base/named.hh"
41#include "base/types.hh"
42#include "cpu/inst_seq.hh"
43
45
47class Base;
48}
49
50namespace gem5
51{
52
53namespace o3
54{
55
57{
58 bool
59 operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
60 {
61 return lhs > rhs;
62 }
63};
64
65
73class StoreSet : public Named
74{
75 public:
76 typedef Addr SSID;
77
78 class SSITEntry : public CacheEntry
79 {
80 private:
82 public:
83 using TagExtractor = std::function<Addr(Addr)>;
84
86
87 void setSSID(SSID id) { _ssid = id; }
88 SSID getSSID(void) const { return _ssid; }
89 };
90
92 StoreSet() : Named("StoreSets"), SSIT("SSIT") {};
93
95 StoreSet(std::string_view name, uint64_t clear_period,
96 size_t SSIT_entries, int SSIT_assoc,
97 replacement_policy::Base *replPolicy,
98 BaseIndexingPolicy *indexingPolicy, int LFST_size);
99
101 ~StoreSet();
102
104 void init(uint64_t clear_period,
105 size_t SSIT_entries, int SSIT_assoc,
106 replacement_policy::Base *_replPolicy,
107 BaseIndexingPolicy *_indexingPolicy, int LFST_size);
108
111 void violation(Addr store_PC, Addr load_PC);
112
117 void checkClear();
118
122 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
123
126 void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid);
127
133
135 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
136
138 void squash(InstSeqNum squashed_num, ThreadID tid);
139
141 void clear();
142
144 void dump();
145
146 private:
148 inline SSID calcSSID(Addr PC)
149 { return ((PC ^ (PC >> 10)) % LFSTSize); }
150
153
156
159
163 std::map<InstSeqNum, int, ltseqnum> storeList;
164
165 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
166
170 uint64_t clearPeriod;
171
174
177
180};
181
182} // namespace o3
183
184} // namespace gem5
185
186#endif // __CPU_O3_STORE_SET_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
CacheEntry(TagExtractor ext)
Named(std::string_view name_)
Definition named.hh:57
std::function< Addr(Addr)> TagExtractor
Definition store_set.hh:83
SSITEntry(TagExtractor ext)
Definition store_set.hh:85
void insertLoad(Addr load_PC, InstSeqNum load_seq_num)
Inserts a load into the store set predictor.
Definition store_set.cc:193
void checkClear()
Clears the store set predictor every so often so that all the entries aren't used and stores are cons...
Definition store_set.cc:181
std::vector< InstSeqNum > LFST
Last Fetched Store Table.
Definition store_set.hh:155
void squash(InstSeqNum squashed_num, ThreadID tid)
Squashes for a specific thread until the given sequence number.
Definition store_set.cc:301
uint64_t clearPeriod
Number of loads/stores to process before wiping predictor so all entries don't get saturated.
Definition store_set.hh:170
void dump()
Debug function to dump the contents of the store list.
Definition store_set.cc:343
void clear()
Resets all tables.
Definition store_set.cc:331
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
Inserts a store into the store set predictor.
Definition store_set.cc:201
~StoreSet()
Default destructor.
Definition store_set.cc:78
SSID calcSSID(Addr PC)
Calculates a Store Set ID based on the PC.
Definition store_set.hh:148
std::vector< bool > validLFST
Bit vector to tell if the LFST has a valid entry.
Definition store_set.hh:158
int LFSTSize
Last Fetched Store Table size, in entries.
Definition store_set.hh:176
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
Records this PC/sequence number as issued.
Definition store_set.cc:265
InstSeqNum checkInst(Addr PC)
Checks if the instruction with the given PC is dependent upon any store.
Definition store_set.cc:232
AssociativeCache< SSITEntry > SSIT
The Store Set ID Table.
Definition store_set.hh:152
std::map< InstSeqNum, int, ltseqnum >::iterator SeqNumMapIt
Definition store_set.hh:165
int SSITSize
Store Set ID Table size, in entries.
Definition store_set.hh:173
StoreSet()
Default constructor.
Definition store_set.hh:92
void violation(Addr store_PC, Addr load_PC)
Records a memory ordering violation between the younger load and the older store.
Definition store_set.cc:112
std::map< InstSeqNum, int, ltseqnum > storeList
Map of stores that have been inserted into the store set, but not yet issued or squashed.
Definition store_set.hh:163
int memOpsPred
Number of memory operations predicted since last clear of predictor.
Definition store_set.hh:179
A common base class of cache replacement policy objects.
Definition base.hh:55
STL vector class.
Definition stl.hh:37
Bitfield< 33 > id
Bitfield< 12 > ext
const FlagsType init
This Stat is Initialized.
Definition info.hh:55
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
IndexingPolicyTemplate< AddrTypes > BaseIndexingPolicy
Definition base.hh:215
const Addr MaxAddr
Definition types.hh:171
uint64_t InstSeqNum
Definition inst_seq.hh:40
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
Definition store_set.hh:59
const std::string & name()
Definition trace.cc:48

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