gem5::BaseCache::CacheAccessorImpl Struct Reference

#include <base.hh>

Inheritance diagram for gem5::BaseCache::CacheAccessorImpl:

Public Member Functions
	CacheAccessorImpl (BaseCache &_cache)
bool	inCache (Addr addr, bool is_secure) const override
	Determine if address is in cache.
bool	hasBeenPrefetched (Addr addr, bool is_secure) const override
	Determine if address has been prefetched.
bool	hasBeenPrefetched (Addr addr, bool is_secure, RequestorID requestor) const override
	Determine if address has been prefetched by the requestor.
bool	inMissQueue (Addr addr, bool is_secure) const override
	Determine if address is in cache miss queue.
bool	coalesce () const override
	Determine if cache is coalescing writes.
Public Member Functions inherited from gem5::CacheAccessor
virtual	~CacheAccessor ()=default

Public Attributes
BaseCache &	cache

Detailed Description

Definition at line 326 of file base.hh.

Constructor & Destructor Documentation

CacheAccessorImpl()

gem5::BaseCache::CacheAccessorImpl::CacheAccessorImpl ( BaseCache & _cache )

inline

Definition at line 330 of file base.hh.

References gem5::BaseCache::BaseCache(), and cache.

Member Function Documentation

coalesce()

bool gem5::BaseCache::CacheAccessorImpl::coalesce ( ) const

inlineoverridevirtual

Determine if cache is coalescing writes.

Implements gem5::CacheAccessor.

Definition at line 345 of file base.hh.

References cache.

hasBeenPrefetched() [1/2]

bool gem5::BaseCache::CacheAccessorImpl::hasBeenPrefetched ( Addr addr, bool is_secure ) const

inlineoverridevirtual

Determine if address has been prefetched.

Implements gem5::CacheAccessor.

Definition at line 335 of file base.hh.

References gem5::X86ISA::addr, and cache.

hasBeenPrefetched() [2/2]

bool gem5::BaseCache::CacheAccessorImpl::hasBeenPrefetched ( Addr addr, bool is_secure, RequestorID requestor ) const

inlineoverridevirtual

Determine if address has been prefetched by the requestor.

Implements gem5::CacheAccessor.

Definition at line 338 of file base.hh.

References gem5::X86ISA::addr, and cache.

inCache()

bool gem5::BaseCache::CacheAccessorImpl::inCache ( Addr addr, bool is_secure ) const

inlineoverridevirtual

Determine if address is in cache.

Implements gem5::CacheAccessor.

Definition at line 332 of file base.hh.

References gem5::X86ISA::addr, and cache.

inMissQueue()

bool gem5::BaseCache::CacheAccessorImpl::inMissQueue ( Addr addr, bool is_secure ) const

inlineoverridevirtual

Determine if address is in cache miss queue.

Implements gem5::CacheAccessor.

Definition at line 342 of file base.hh.

References gem5::X86ISA::addr, and cache.

Member Data Documentation

cache

BaseCache& gem5::BaseCache::CacheAccessorImpl::cache

Definition at line 328 of file base.hh.

Referenced by CacheAccessorImpl(), coalesce(), hasBeenPrefetched(), hasBeenPrefetched(), inCache(), and inMissQueue().

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The documentation for this struct was generated from the following file:

• mem/cache/base.hh