gem5::VegaISA::InFmt_MTBUF_1 Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	VADDR: 8
unsigned int	VDATA: 8
unsigned int	SRSRC: 5
unsigned int	pad_21: 1
unsigned int	SLC: 1
unsigned int	TFE: 1
unsigned int	SOFFSET: 8

Detailed Description

Definition at line 1871 of file gpu_decoder.hh.

Member Data Documentation

pad_21

unsigned int gem5::VegaISA::InFmt_MTBUF_1::pad_21

Definition at line 1875 of file gpu_decoder.hh.

SLC

unsigned int gem5::VegaISA::InFmt_MTBUF_1::SLC

Definition at line 1876 of file gpu_decoder.hh.

SOFFSET

unsigned int gem5::VegaISA::InFmt_MTBUF_1::SOFFSET

Definition at line 1878 of file gpu_decoder.hh.

SRSRC

unsigned int gem5::VegaISA::InFmt_MTBUF_1::SRSRC

Definition at line 1874 of file gpu_decoder.hh.

TFE

unsigned int gem5::VegaISA::InFmt_MTBUF_1::TFE

Definition at line 1877 of file gpu_decoder.hh.

VADDR

unsigned int gem5::VegaISA::InFmt_MTBUF_1::VADDR

Definition at line 1872 of file gpu_decoder.hh.

VDATA

unsigned int gem5::VegaISA::InFmt_MTBUF_1::VDATA

Definition at line 1873 of file gpu_decoder.hh.

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh