gem5::VegaISA::InFmt_SOP2 Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SSRC0: 8
unsigned int	SSRC1: 8
unsigned int	SDST: 7
unsigned int	OP: 7
unsigned int	ENCODING: 2

Detailed Description

Definition at line 1836 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::VegaISA::InFmt_SOP2::ENCODING

Definition at line 1841 of file gpu_decoder.hh.

OP

unsigned int gem5::VegaISA::InFmt_SOP2::OP

Definition at line 1840 of file gpu_decoder.hh.

SDST

unsigned int gem5::VegaISA::InFmt_SOP2::SDST

Definition at line 1839 of file gpu_decoder.hh.

SSRC0

unsigned int gem5::VegaISA::InFmt_SOP2::SSRC0

Definition at line 1837 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP2::hasSecondDword().

SSRC1

unsigned int gem5::VegaISA::InFmt_SOP2::SSRC1

Definition at line 1838 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP2::hasSecondDword().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh