gem5::VegaISA::InFmt_VOP_SDWA Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SRC0: 8
unsigned int	DST_SEL: 3
unsigned int	DST_U: 2
unsigned int	CLMP: 1
unsigned int	OMOD: 2
unsigned int	SRC0_SEL: 3
unsigned int	SRC0_SEXT: 1
unsigned int	SRC0_NEG: 1
unsigned int	SRC0_ABS: 1
unsigned int	pad_22: 1
unsigned int	S0: 1
unsigned int	SRC1_SEL: 3
unsigned int	SRC1_SEXT: 1
unsigned int	SRC1_NEG: 1
unsigned int	SRC1_ABS: 1
unsigned int	pad_30: 1
unsigned int	S1: 1

Detailed Description

Definition at line 1933 of file gpu_decoder.hh.

Member Data Documentation

CLMP

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::CLMP

Definition at line 1937 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_dst().

DST_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::DST_SEL

Definition at line 1935 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_dst().

DST_U

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::DST_U

Definition at line 1936 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_dst().

OMOD

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::OMOD

Definition at line 1938 of file gpu_decoder.hh.

pad_22

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::pad_22

Definition at line 1943 of file gpu_decoder.hh.

pad_30

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::pad_30

Definition at line 1949 of file gpu_decoder.hh.

S0

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::S0

Definition at line 1944 of file gpu_decoder.hh.

S1

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::S1

Definition at line 1950 of file gpu_decoder.hh.

SRC0

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0

Definition at line 1934 of file gpu_decoder.hh.

SRC0_ABS

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_ABS

Definition at line 1942 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC0_NEG

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_NEG

Definition at line 1941 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC0_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEL

Definition at line 1939 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC0_SEXT

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEXT

Definition at line 1940 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC1_ABS

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_ABS

Definition at line 1948 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC1_NEG

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_NEG

Definition at line 1947 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

SRC1_SEL

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEL

Definition at line 1945 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src().

SRC1_SEXT

unsigned int gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEXT

Definition at line 1946 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::processSDWA_src(), and gem5::VegaISA::processSDWA_src().

---

The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh