#include <i8254xGBe_defs.hh>
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| | ADD_FIELD32 (eep_fw_semaphore, 0, 1) |
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| | ADD_FIELD32 (fw_mode, 1, 3) |
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| | ADD_FIELD32 (ide, 4, 1) |
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| | ADD_FIELD32 (sol, 5, 1) |
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| | ADD_FIELD32 (eep_roload, 6, 1) |
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| | ADD_FIELD32 (reserved, 7, 8) |
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| | ADD_FIELD32 (fw_val_bit, 15, 1) |
| |
| | ADD_FIELD32 (reset_cnt, 16, 3) |
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| | ADD_FIELD32 (ext_err_ind, 19, 6) |
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| | ADD_FIELD32 (reserved2, 25, 7) |
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| uint32_t | operator() () |
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| void | operator() (uint32_t d) |
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| const Reg< uint32_t > & | operator= (uint32_t d) |
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| bool | operator== (uint32_t d) |
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| | Reg () |
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| void | serialize (CheckpointOut &cp) const |
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| void | unserialize (CheckpointIn &cp) |
| |
Definition at line 948 of file i8254xGBe_defs.hh.
◆ ADD_FIELD32() [1/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
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eep_fw_semaphore | , |
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0 | , |
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1 | ) |
◆ ADD_FIELD32() [2/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
eep_roload | , |
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6 | , |
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1 | ) |
◆ ADD_FIELD32() [3/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
ext_err_ind | , |
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19 | , |
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6 | ) |
◆ ADD_FIELD32() [4/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
fw_mode | , |
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1 | , |
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3 | ) |
◆ ADD_FIELD32() [5/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
fw_val_bit | , |
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15 | , |
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1 | ) |
◆ ADD_FIELD32() [6/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
ide | , |
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4 | , |
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1 | ) |
◆ ADD_FIELD32() [7/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
reserved | , |
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7 | , |
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8 | ) |
◆ ADD_FIELD32() [8/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
reserved2 | , |
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25 | , |
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7 | ) |
◆ ADD_FIELD32() [9/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
reset_cnt | , |
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16 | , |
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3 | ) |
◆ ADD_FIELD32() [10/10]
| gem5::igbreg::Regs::FWSM::ADD_FIELD32 |
( |
sol | , |
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5 | , |
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1 | ) |
The documentation for this struct was generated from the following file: