In a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache. More...

Public Member Functions
	DelayQueueEntry (Addr x, Tick t)

Public Attributes
Addr	baseAddr

Tick	processTick

Detailed Description

In a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache.

Adding the delay queue tries to avoid always striving for timeless prefetches, which has been found to not always being optimal.

Definition at line 100 of file bop.hh.

Constructor & Destructor Documentation

◆ DelayQueueEntry()

gem5::prefetch::BOP::DelayQueueEntry::DelayQueueEntry	(	Addr	x,
		Tick	t )

inline

Definition at line 105 of file bop.hh.

References baseAddr, processTick, gem5::ArmISA::t, and gem5::RiscvISA::x.

Member Data Documentation

◆ baseAddr

Addr gem5::prefetch::BOP::DelayQueueEntry::baseAddr

Definition at line 102 of file bop.hh.

Referenced by DelayQueueEntry().

◆ processTick

Tick gem5::prefetch::BOP::DelayQueueEntry::processTick

Definition at line 103 of file bop.hh.