gem5 [DEVELOP-FOR-25.0]
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display.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 display.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38#include "common.h"
39
40/****************************************************************/
42/****************************************************************/
43
44ofstream lout ("systemc.log"); // Output log file
45
46/******************************************************************************/
47/*************************** Output Display Function **********************/
48/******************************************************************************/
49
50SC_MODULE( DISPLAY )
51{
52 SC_HAS_PROCESS( DISPLAY );
53
54// INPUTS & OUTPUTS TO DISPLAY
55
56 const sc_signal<bool>& reset;
57 const sc_signal<bool>& in_ok;
58 const sc_signal<bool>& out_ok;
59 const sc_signal<bool>& instrb;
60 const sc_signal<bool>& outstrb;
61 const signal_bool_vector &a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;
62 const signal_bool_vector &d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8;
63
64// CONSTRUCTOR DEFINITION
65
66 DISPLAY( sc_module_name NAME,
67 const sc_signal<bool>& RESET,
68 const sc_signal<bool>& IN_OK,
69 const sc_signal<bool>& OUT_OK,
70 const sc_signal<bool>& INSTRB,
71 const sc_signal<bool>& OUTSTRB,
72 const signal_bool_vector& A1,
73 const signal_bool_vector& A2,
74 const signal_bool_vector& A3,
75 const signal_bool_vector& A4,
76 const signal_bool_vector& A5,
77 const signal_bool_vector& A6,
78 const signal_bool_vector& A7,
79 const signal_bool_vector& A8,
80 const signal_bool_vector& D1,
81 const signal_bool_vector& D2,
82 const signal_bool_vector& D3,
83 const signal_bool_vector& D4,
84 const signal_bool_vector& D5,
85 const signal_bool_vector& D6,
86 const signal_bool_vector& D7,
87 const signal_bool_vector& D8
88 )
89
90 :
91 reset (RESET),
92 in_ok (IN_OK),
93 out_ok (OUT_OK),
94 instrb (INSTRB),
95 outstrb (OUTSTRB),
96 a1 (A1), a2(A2), a3(A3), a4(A4),
97 a5 (A5), a6(A6), a7(A7), a8(A8),
98 d1 (D1), d2(D2), d3(D3), d4(D4),
99 d5 (D5), d6(D6), d7(D7), d8(D8)
100
101 {
102 SC_METHOD( entry );
103 sensitive << reset;
104 sensitive << in_ok;
105 sensitive << out_ok;
106 sensitive << instrb;
107 sensitive << outstrb;
108 sensitive << a1;
109 sensitive << a2;
110 sensitive << a3;
111 sensitive << a4;
112 sensitive << a5;
113 sensitive << a6;
114 sensitive << a7;
115 sensitive << a8;
116 sensitive << d1;
117 sensitive << d2;
118 sensitive << d3;
119 sensitive << d4;
120 sensitive << d5;
121 sensitive << d6;
122 sensitive << d7;
123 sensitive << d8;
124 }
125
126 /*** Call to Process Functionality ***/
127 void entry();
128
129};
130
131void
132DISPLAY::entry()
133{
134// DISPLAYS ALL SIGNALS USED TO DEBUG DESIGN
135
136 lout << " reset = " << reset
137 << " in_ok = " << in_ok
138 << " out_ok = " << out_ok
139 << " instrb = " << instrb
140 << " outstrb = " << outstrb
141 << "\n"
142 << " a1 = " << a1
143 << " a2 = " << a2
144 << " a3 = " << a3
145 << " a4 = " << a4
146 << "\n"
147 << " a5 = " << a5
148 << " a6 = " << a6
149 << " a7 = " << a7
150 << " a8 = " << a8
151 << "\n"
152 << " d1 = " << d1
153 << " d2 = " << d2
154 << " d3 = " << d3
155 << " d4 = " << d4
156 << "\n"
157 << " d5 = " << d5
158 << " d6 = " << d6
159 << " d7 = " << d7
160 << " d8 = " << d8
161 << endl;
162
163}
sc_module_name
Definition sc_module_name.hh:42
sc_signal
Definition sc_signal.hh:273
gem5::ArmISA::a1
Bitfield< 22 > a1
Definition misc_types.hh:587
gem5::PowerISA::d1
Bitfield< 20, 16 > d1
Definition types.hh:66
gem5::PowerISA::d2
Bitfield< 1, 0 > d2
Definition types.hh:67
SC_METHOD
#define SC_METHOD(name)
Definition sc_module.hh:303
SC_MODULE
#define SC_MODULE(name)
Definition sc_module.hh:295
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition common.h:44
lout
ofstream lout("systemc.log")
Display to standard out and to logfile "systemc.log".
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