gem5
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systemc
tests
systemc
misc
synth
bubble
stim.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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stim.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/******************************************************************************/
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/*************************** stimulus Class Definition ********************/
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/******************************************************************************/
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#include "
common.h
"
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SC_MODULE
( STIM )
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{
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SC_HAS_PROCESS
( STIM );
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sc_in_clk
clk;
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sc_signal<bool>
& reset;
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sc_signal<bool>
& in_ok;
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sc_signal<bool>
& out_ok;
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const
sc_signal<bool>
& instrb;
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const
sc_signal<bool>
& outstrb;
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signal_bool_vector
&a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;
// -128 to 127
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const
signal_bool_vector
&d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8;
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STIM(
sc_module_name
NAME,
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sc_clock
& TICK_P,
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sc_signal<bool>
& RESET,
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sc_signal<bool>
& IN_OK,
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sc_signal<bool>
& OUT_OK,
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const
sc_signal<bool>
& INSTRB,
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const
sc_signal<bool>
& OUTSTRB,
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signal_bool_vector
& A1,
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signal_bool_vector
& A2,
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signal_bool_vector
& A3,
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signal_bool_vector
& A4,
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signal_bool_vector
& A5,
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signal_bool_vector
& A6,
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signal_bool_vector
& A7,
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signal_bool_vector
& A8,
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signal_bool_vector
& D1,
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signal_bool_vector
& D2,
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signal_bool_vector
& D3,
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signal_bool_vector
& D4,
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signal_bool_vector
& D5,
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signal_bool_vector
& D6,
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signal_bool_vector
& D7,
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signal_bool_vector
& D8
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)
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:
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reset (RESET),
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in_ok (IN_OK),
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out_ok (OUT_OK),
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instrb (INSTRB),
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outstrb (OUTSTRB),
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a1 (A1), a2(A2), a3(A3), a4(A4),
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a5 (A5), a6(A6), a7(A7), a8(A8),
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d1 (D1), d2(D2), d3(D3), d4(D4),
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d5 (D5), d6(D6), d7(D7), d8(D8)
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{
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clk(TICK_P);
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SC_CTHREAD
( entry, clk.neg() );
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}
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void
entry();
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};
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/******************************************************************************/
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/*************************** testbench Entry Function **********************/
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/******************************************************************************/
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void
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STIM::entry()
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{
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// INITIAL INPUT VALUES
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a1
.write(0);
// Are quotes necessary ???
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a2.write(0);
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a3.write(0);
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a4.write(0);
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a5.write(0);
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a6.write(0);
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a7.write(0);
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a8.write(0);
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in_ok.write(0);
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out_ok.write(0);
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reset
.write(1);
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wait
(2);
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// REMOVE RESET
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reset
.write(0);
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wait
();
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// WAIT FOR REQUEST FOR INPUT
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do
{
wait
(); }
while
(instrb == 0);
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// SEND INPUT DATA TO BE SORTED
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a1
.write(-76);
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a2.write( 1);
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a3.write( 12);
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a4.write( 85);
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a5.write( 15);
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a6.write(103);
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a7.write( -2);
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a8.write( 3);
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in_ok.write(1);
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wait
();
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// WAIT FOR OUTPUT READY
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do
{
wait
(); }
while
(outstrb == 0);
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// READ OUTPUT & DISPLAY RESULTS
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cout <<
"\n"
<< endl;
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cout <<
"\t\t INPUT DATA \t\t SORTED DATA"
<< endl;
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cout <<
"\t\t "
<<
a1
.read().to_int() <<
" \t\t "
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<<
d1
.read().to_int() << endl;
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cout <<
"\t\t "
<< a2.read().to_int() <<
" \t\t "
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<<
d2
.read().to_int() << endl;
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cout <<
"\t\t "
<< a3.read().to_int() <<
" \t\t "
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<< d3.read().to_int() << endl;
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cout <<
"\t\t "
<< a4.read().to_int() <<
" \t\t "
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<< d4.read().to_int() << endl;
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cout <<
"\t\t "
<< a5.read().to_int() <<
" \t\t "
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<< d5.read().to_int() << endl;
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cout <<
"\t\t "
<< a6.read().to_int() <<
" \t\t "
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<< d6.read().to_int() << endl;
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cout <<
"\t\t "
<< a7.read().to_int() <<
" \t\t "
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<< d7.read().to_int() << endl;
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cout <<
"\t\t "
<< a8.read().to_int() <<
" \t\t "
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<< d8.read().to_int() << endl;
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cout <<
"\n"
<< endl;
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// SEND FINISHED READING OUTPUT FLAG
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in_ok.write(0);
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out_ok.write(1);
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wait
();
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// STOP SIMULATION
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sc_stop
();
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}
sc_in_clk
sc_in< bool > sc_in_clk
Definition
sc_clock.hh:116
sc_clock
Definition
sc_clock.hh:50
sc_module_name
Definition
sc_module_name.hh:42
sc_signal
Definition
sc_signal.hh:273
sc_stop
void sc_stop()
Definition
sc_main.cc:103
wait
void wait()
Definition
sc_module.cc:653
gem5::ArmISA::a1
Bitfield< 22 > a1
Definition
misc_types.hh:587
gem5::PowerISA::d1
Bitfield< 20, 16 > d1
Definition
types.hh:66
gem5::PowerISA::d2
Bitfield< 1, 0 > d2
Definition
types.hh:67
gem5::statistics::reset
void reset()
Definition
statistics.cc:309
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition
sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition
sc_module.hh:295
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition
sc_module.hh:301
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition
common.h:44
common.h
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