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gem5 [DEVELOP-FOR-25.0]
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#include <memory>#include "arch/arm/regs/misc.hh"#include "arch/arm/tracers/tarmac_base.hh"#include "base/printable.hh"#include "cpu/reg_class.hh"#include "cpu/static_inst.hh"Go to the source code of this file.
Classes | |
| class | gem5::trace::TarmacTracerRecord |
| TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction. More... | |
| struct | gem5::trace::TarmacTracerRecord::TraceInstEntry |
| Instruction Entry. More... | |
| struct | gem5::trace::TarmacTracerRecord::TraceRegEntry |
| Register Entry. More... | |
| struct | gem5::trace::TarmacTracerRecord::TraceMemEntry |
| Memory Entry. More... | |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
| namespace | gem5::trace |
Functions | |
| std::string | gem5::trace::iSetStateToStr (TarmacBaseRecord::ISetState isetstate) |
| Returns the string representation of the instruction set being currently run according to the Tarmac format. | |
| std::string | gem5::trace::opModeToStr (ArmISA::OperatingMode opMode) |
| Returns the string representation of the ARM Operating Mode (CPSR.M[3:0] field) according to the Tarmac format. | |