zcmt.cc

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#include "arch/riscv/insts/zcmt.hh"
 
#include <string>
 
#include "arch/riscv/pcstate.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/utility.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
ZcmtSecondFetchInst::ZcmtSecondFetchInst(ExtMachInst machInst, Addr entry)
    : RiscvStaticInst("cm.jalt", machInst, IntAluOp), jvtEntry(entry)
{
    setRegIdxArrays(
        reinterpret_cast<RegIdArrayPtr>(
            &std::remove_pointer_t<decltype(this)>::srcRegIdxArr),
        reinterpret_cast<RegIdArrayPtr>(
            &std::remove_pointer_t<decltype(this)>::destRegIdxArr));
    flags[IsControl] = true;
    flags[IsDirectControl] = true;
    flags[IsInteger] = true;
    flags[IsUncondControl] = true;
}
 
Fault
ZcmtSecondFetchInst::execute(
    ExecContext *xc, trace::InstRecord *traceData) const
{
    PCState jvtPCState;
    set(jvtPCState, xc->pcState());
    jvtPCState.npc(rvSext(jvtEntry & ~0x1));
    jvtPCState.zcmtSecondFetch(false);
    jvtPCState.zcmtPc(0);
    xc->pcState(jvtPCState);
    return NoFault;
}
 
std::string
ZcmtSecondFetchInst::generateDisassembly(
    Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    ss << mnemonic << " jvt entry (" << std::hex << rvSext(jvtEntry & ~0x1)
       << ")";
    return ss.str();
}
 
std::unique_ptr<PCStateBase>
ZcmtSecondFetchInst::branchTarget(
    const PCStateBase &branch_pc) const
{
    auto &rpc = branch_pc.as<RiscvISA::PCState>();
    std::unique_ptr<PCState> npc(dynamic_cast<PCState*>(rpc.clone()));
    npc->zcmtSecondFetch(false);
    npc->zcmtPc(0);
    npc->set(rvSext(jvtEntry & ~0x1));
    return npc;
}
 
} // namespace RiscvISA
} // namespace gem5