#include <zcmt.hh>

Inheritance diagram for gem5::RiscvISA::ZcmtSecondFetchInst:

Public Member Functions
	ZcmtSecondFetchInst (ExtMachInst machInst, Addr entry)
	Constructor.

Fault	execute (ExecContext , trace::InstRecord ) const override

std::string	generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override
	Internal function to generate disassembly string.

std::unique_ptr< PCStateBase >	branchTarget (const PCStateBase &branch_pc) const override
	Return the target address for a PC-relative branch.

virtual std::unique_ptr< PCStateBase >	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump).

Public Member Functions inherited from gem5::RiscvISA::RiscvStaticInst
void	advancePC (PCStateBase &pc) const override

void	advancePC (ThreadContext *tc) const override

uint64_t	getEMI () const override

std::unique_ptr< PCStateBase >	buildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override

size_t	asBytes (void *buf, size_t size) override
	Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

Public Member Functions inherited from gem5::StaticInst
uint8_t	numSrcRegs () const
	Number of source registers.

uint8_t	numDestRegs () const
	Number of destination registers.

uint8_t	numDestRegs (RegClassType type) const
	Number of destination registers of a particular type.

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isMatrix () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isFullMemBarrier () const

bool	isReadBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isUnverifiable () const

bool	isPseudo () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isHtmStart () const

bool	isHtmStop () const

bool	isHtmCancel () const

bool	isInvalid () const

bool	isHtmCmd () const

void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue.

const RegId &	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg.

void	setDestRegIdx (int i, const RegId &val)

const RegId &	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg.

void	setSrcRegIdx (int i, const RegId &val)

virtual	~StaticInst ()

virtual Fault	initiateAcc (ExecContext xc, trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, trace::InstRecord *trace_data) const

size_t	size () const

virtual void	size (size_t newSize)

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc.

virtual const std::string &	disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const
	Return string representation of disassembled instruction.

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream.

std::string	getName ()
	Return name of machine instruction.

Public Member Functions inherited from gem5::RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one.

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects.

void	incref () const
	Increment the reference count.

void	decref () const
	Decrement the reference count and destroy the object if all references are gone.

Private Attributes
RegId	srcRegIdxArr [0]

RegId	destRegIdxArr [0]

Addr	jvtEntry

Additional Inherited Members
Public Types inherited from gem5::StaticInst
using	RegIdArrayPtr = RegId (StaticInst:: *)[]

Public Attributes inherited from gem5::RiscvISA::RiscvStaticInst
ExtMachInst	machInst

static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object.

Protected Member Functions inherited from gem5::RiscvISA::RiscvStaticInst
	RiscvStaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)

template<typename T>
T	rvSelect (T v32, T v64) const

template<typename T32, typename T64>
T64	rvExt (T64 x) const

uint64_t	rvZext (uint64_t x) const

int64_t	rvSext (int64_t x) const

void	setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
	Set the pointers which point to the arrays of source and destination register indices.

	StaticInst (const char *_mnemonic, OpClass op_class)
	Constructor.

template<typename T>
size_t	simpleAsBytes (void *buf, size_t max_size, const T &t)

Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags >	flags
	Flag values for this instruction.

OpClass	_opClass
	See opClass().

uint8_t	_numSrcRegs = 0
	See numSrcRegs().

uint8_t	_numDestRegs = 0
	See numDestRegs().

std::array< uint8_t, MiscRegClass+1 >	_numTypedDestRegs = {}

size_t	_size = 0
	Instruction size in bytes.

const char *	mnemonic
	Base mnemonic (e.g., "add").

std::unique_ptr< std::string >	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()).

Detailed Description

Definition at line 43 of file zcmt.hh.

Constructor & Destructor Documentation

◆ ZcmtSecondFetchInst()

gem5::RiscvISA::ZcmtSecondFetchInst::ZcmtSecondFetchInst	(	ExtMachInst	machInst,
		Addr	entry )

Constructor.

Definition at line 43 of file zcmt.cc.

References destRegIdxArr, gem5::StaticInst::flags, gem5::IntAluOp, jvtEntry, gem5::RiscvISA::RiscvStaticInst::machInst, gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst(), gem5::StaticInst::setRegIdxArrays(), and srcRegIdxArr.

Member Function Documentation

◆ branchTarget() [1/2]

std::unique_ptr< PCStateBase > gem5::RiscvISA::ZcmtSecondFetchInst::branchTarget ( const PCStateBase & pc ) const

overridevirtual

Return the target address for a PC-relative branch.

Invalid if not a PC-relative branch (i.e. isDirectCtrl() should be true).

Reimplemented from gem5::StaticInst.

Definition at line 81 of file zcmt.cc.

References gem5::PCStateBase::as(), jvtEntry, and gem5::RiscvISA::RiscvStaticInst::rvSext().

◆ branchTarget() [2/2]

std::unique_ptr< PCStateBase > gem5::StaticInst::branchTarget ( ThreadContext * tc ) const

virtual

Return the target address for an indirect branch (jump).

The register value is read from the supplied thread context, so the result is valid only if the thread context is about to execute the branch in question. Invalid if not an indirect branch (i.e. isIndirectCtrl() should be true).

Reimplemented from gem5::StaticInst.

Definition at line 351 of file static_inst.cc.

◆ execute()

Fault gem5::RiscvISA::ZcmtSecondFetchInst::execute	(	ExecContext *	xc,
		trace::InstRecord *	traceData ) const

overridevirtual

Implements gem5::StaticInst.

Definition at line 58 of file zcmt.cc.

References jvtEntry, gem5::NoFault, gem5::GenericISA::PCStateWithNext::npc(), gem5::ExecContext::pcState(), gem5::RiscvISA::RiscvStaticInst::rvSext(), gem5::ArmISA::set, gem5::RiscvISA::PCState::zcmtPc(), and gem5::RiscvISA::PCState::zcmtSecondFetch().

◆ generateDisassembly()

std::string gem5::RiscvISA::ZcmtSecondFetchInst::generateDisassembly	(	Addr	pc,
		const loader::SymbolTable *	symtab ) const

overridevirtual

Internal function to generate disassembly string.

Implements gem5::StaticInst.

Definition at line 71 of file zcmt.cc.

References jvtEntry, gem5::StaticInst::mnemonic, gem5::RiscvISA::pc, gem5::RiscvISA::RiscvStaticInst::rvSext(), and gem5::RiscvISA::ss.

Member Data Documentation

◆ destRegIdxArr

RegId gem5::RiscvISA::ZcmtSecondFetchInst::destRegIdxArr[0]

private

Definition at line 47 of file zcmt.hh.

Referenced by ZcmtSecondFetchInst().

◆ jvtEntry

Addr gem5::RiscvISA::ZcmtSecondFetchInst::jvtEntry

private

Definition at line 48 of file zcmt.hh.

Referenced by branchTarget(), execute(), generateDisassembly(), and ZcmtSecondFetchInst().

◆ srcRegIdxArr

RegId gem5::RiscvISA::ZcmtSecondFetchInst::srcRegIdxArr[0]

private

Definition at line 46 of file zcmt.hh.

Referenced by ZcmtSecondFetchInst().

The documentation for this class was generated from the following files:

arch/riscv/insts/zcmt.hh
arch/riscv/insts/zcmt.cc

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ZcmtSecondFetchInst()

Member Function Documentation

◆ branchTarget() [1/2]

◆ branchTarget() [2/2]

◆ execute()

◆ generateDisassembly()

Member Data Documentation

◆ destRegIdxArr

◆ jvtEntry

◆ srcRegIdxArr