faults.hh File Reference

#include <cstdint>
#include <string>
#include "arch/riscv/fault_codes.hh"
#include "arch/riscv/isa.hh"
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"

Go to the source code of this file.

Classes
class	gem5::RiscvISA::RiscvFault
class	gem5::RiscvISA::Reset
class	gem5::RiscvISA::InterruptFault
class	gem5::RiscvISA::NonMaskableInterruptFault
class	gem5::RiscvISA::InstFault
class	gem5::RiscvISA::VirtualInstFault
class	gem5::RiscvISA::UnknownInstFault
class	gem5::RiscvISA::IllegalInstFault
class	gem5::RiscvISA::UnimplementedFault
class	gem5::RiscvISA::IllegalFrmFault
class	gem5::RiscvISA::AddressFault
class	gem5::RiscvISA::BreakpointFault
class	gem5::RiscvISA::SyscallFault

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA

Enumerations
enum class	gem5::RiscvISA::FaultType { gem5::RiscvISA::INTERRUPT , gem5::RiscvISA::NON_MASKABLE_INTERRUPT , gem5::RiscvISA::OTHERS }

Functions
bool	gem5::RiscvISA::getFaultVAddr (Fault fault, Addr &va)
	Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.