gem5::RiscvISA Namespace Reference

Namespaces
namespace	float_reg
namespace	int_reg

Classes
class	AddressFault
class	AtomicGenericOp
	A generic atomic op class. More...
class	AtomicMemOp
class	AtomicMemOpMicro
class	BareMetal
class	BasePMAChecker
	Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the Physical Memory Attributes. More...
class	BootloaderKernelWorkload
class	BreakpointFault
class	BSOp
class	CmMacroInst
class	CompRegOp
	Base class for compressed operations that work only on registers. More...
struct	CSRMetadata
class	CSROp
	Base class for CSR operations. More...
class	Decoder
struct	double_width
struct	double_width< float16_t >
struct	double_width< float32_t >
struct	double_width< float8_t >
struct	double_width< int16_t >
struct	double_width< int32_t >
struct	double_width< int64_t >
struct	double_width< int8_t >
struct	double_width< uint16_t >
struct	double_width< uint32_t >
struct	double_width< uint64_t >
struct	double_width< uint8_t >
struct	double_widthf
struct	double_widthf< int16_t >
struct	double_widthf< int32_t >
struct	double_widthf< int8_t >
struct	double_widthf< uint16_t >
struct	double_widthf< uint32_t >
struct	double_widthf< uint8_t >
class	EmuLinux
class	FsLinux
class	IllegalFrmFault
class	IllegalInstFault
class	ImmOp
	Base class for operations with immediates (I is the type of immediate) More...
class	InstFault
class	InterruptFault
class	Interrupts
class	ISA
class	Load
class	LoadReserved
class	LoadReservedMicro
class	MemAccessInfo
class	MemFenceMicro
class	MemInst
class	MmioVirtIO
class	MMU
class	NonMaskableInterruptFault
class	PCState
class	PMAChecker
	This class provides an abstract PMAChecker for RISC-V to provide PMA checking functionality. More...
class	PMP
	This class helps to implement RISCV's physical memory protection (pmp) primitive. More...
class	PseudoOp
struct	RegABI32
struct	RegABI64
class	RegOp
	Base class for operations that work only on registers. More...
class	RemoteGDB
class	Reset
class	RiscvFault
class	RiscvMacroInst
	Base class for all RISC-V Macroops. More...
class	RiscvMicroInst
	Base class for all RISC-V Microops. More...
class	RiscvStaticInst
	Base class for all RISC-V static instructions. More...
class	SEWorkload
class	StackTrace
class	Store
class	StoreCond
class	StoreCondMicro
class	SyscallFault
class	SystemOp
	Base class for system operations. More...
class	TLB
struct	TlbEntry
class	UnimplementedFault
class	Unknown
	Static instruction class for unknown (illegal) instructions. More...
class	UnknownInstFault
class	VConfOp
	Base class for Vector Config operations. More...
class	VCpyVsMicroInst
class	VectorArithMacroInst
class	VectorArithMicroInst
class	VectorMacroInst
class	VectorMemMacroInst
class	VectorMemMicroInst
class	VectorMicroInst
class	VectorNonSplitInst
class	VectorNopMicroInst
class	VectorSlideMacroInst
class	VectorSlideMicroInst
class	VectorVMUNARY0MacroInst
class	VectorVMUNARY0MicroInst
class	VirtualInstFault
class	VlElementMacroInst
class	VlElementMicroInst
class	VleMacroInst
class	VleMicroInst
class	VlFFTrimVlMicroOp
class	VlIndexMacroInst
class	VlIndexMicroInst
class	VlSegDeIntrlvMicroInst
class	VlSegMacroInst
class	VlSegMicroInst
class	VlWholeMacroInst
class	VlWholeMicroInst
class	VMaskMergeMicroInst
class	VMvWholeMacroInst
class	VMvWholeMicroInst
class	VPinVdMicroInst
class	VsElementMacroInst
class	VsElementMicroInst
class	VseMacroInst
class	VseMicroInst
class	VsIndexMacroInst
class	VsIndexMicroInst
class	VsSegIntrlvMicroInst
class	VsSegMacroInst
class	VsSegMicroInst
class	VsWholeMacroInst
class	VsWholeMicroInst
class	VxsatMicroInst
class	Walker
class	ZcmtSecondFetchInst

Typedefs
using	VPUStatus = FPUStatus
typedef Trie< Addr, TlbEntry >	TlbEntryTrie
using	RiscvType = enums::RiscvType
using	PrivilegeModeSet = enums::PrivilegeModeSet
using	freg_t = float64_t
using	VecRegContainer = gem5::VecRegContainer<MaxVecLenInBytes>
using	vreg_t = VecRegContainer
typedef uint32_t	MachInst

Enumerations
enum	FloatException : uint64_t {   FloatInexact = 0x1 , FloatUnderflow = 0x2 , FloatOverflow = 0x4 , FloatDivZero = 0x8 ,   FloatInvalid = 0x10 }
enum	ExceptionCode : uint64_t {   INST_ADDR_MISALIGNED = 0 , INST_ACCESS = 1 , INST_ILLEGAL = 2 , BREAKPOINT = 3 ,   LOAD_ADDR_MISALIGNED = 4 , LOAD_ACCESS = 5 , STORE_ADDR_MISALIGNED = 6 , AMO_ADDR_MISALIGNED = 6 ,   STORE_ACCESS = 7 , AMO_ACCESS = 7 , ECALL_USER = 8 , ECALL_SUPER = 9 ,   ECALL_VIRTUAL_SUPER = 10 , ECALL_MACHINE = 11 , INST_PAGE = 12 , LOAD_PAGE = 13 ,   STORE_PAGE = 15 , AMO_PAGE = 15 , INST_GUEST_PAGE = 20 , LOAD_GUEST_PAGE = 21 ,   VIRTUAL_INST = 22 , STORE_GUEST_PAGE = 23 , AMO_GUEST_PAGE = 23 , INT_SOFTWARE_SUPER = 1 ,   INT_SOFTWARE_VIRTUAL_SUPER = 2 , INT_SOFTWARE_MACHINE = 3 , INT_TIMER_SUPER = 5 , INT_TIMER_VIRTUAL_SUPER = 6 ,   INT_TIMER_MACHINE = 7 , INT_EXT_SUPER = 9 , INT_EXT_VIRTUAL_SUPER = 10 , INT_EXT_MACHINE = 11 ,   INT_EXT_SUPER_GUEST = 12 , INT_LOCAL_0 = 16 , INT_LOCAL_1 = 17 , INT_LOCAL_2 = 18 ,   INT_LOCAL_3 = 19 , INT_LOCAL_4 = 20 , INT_LOCAL_5 = 21 , INT_LOCAL_6 = 22 ,   INT_LOCAL_7 = 23 , INT_LOCAL_8 = 24 , INT_LOCAL_9 = 25 , INT_LOCAL_10 = 26 ,   INT_LOCAL_11 = 27 , INT_LOCAL_12 = 28 , INT_LOCAL_13 = 29 , INT_LOCAL_14 = 30 ,   INT_LOCAL_15 = 31 , INT_LOCAL_16 = 32 , INT_LOCAL_17 = 33 , INT_LOCAL_18 = 34 ,   INT_LOCAL_19 = 35 , INT_LOCAL_20 = 36 , INT_LOCAL_21 = 37 , INT_LOCAL_22 = 38 ,   INT_LOCAL_23 = 39 , INT_LOCAL_24 = 40 , INT_LOCAL_25 = 41 , INT_LOCAL_26 = 42 ,   INT_LOCAL_27 = 43 , INT_LOCAL_28 = 44 , INT_LOCAL_29 = 45 , INT_LOCAL_30 = 46 ,   INT_LOCAL_31 = 47 , INT_LOCAL_32 = 48 , INT_LOCAL_33 = 49 , INT_LOCAL_34 = 50 ,   INT_LOCAL_35 = 51 , INT_LOCAL_36 = 52 , INT_LOCAL_37 = 53 , INT_LOCAL_38 = 54 ,   INT_LOCAL_39 = 55 , INT_LOCAL_40 = 56 , INT_LOCAL_41 = 57 , INT_LOCAL_42 = 58 ,   INT_LOCAL_43 = 59 , INT_LOCAL_44 = 60 , INT_LOCAL_45 = 61 , INT_LOCAL_46 = 62 ,   INT_LOCAL_47 = 63 , NumInterruptTypes , INT_NMI = NumInterruptTypes }
enum class	FaultType { INTERRUPT , NON_MASKABLE_INTERRUPT , OTHERS }
enum	PrivilegeMode { PRV_U = 0 , PRV_S = 1 , PRV_HS = 2 , PRV_M = 3 }
enum	FPUStatus { OFF = 0 , INITIAL = 1 , CLEAN = 2 , DIRTY = 3 }
enum	XlateFlags { HLVX = 1ULL << 3 , FORCE_VIRT = 1ULL << 4 , LR = 1ULL << 5 }
enum	MiscRegIndex {   MISCREG_PRV = 0 , MISCREG_ISA , MISCREG_VENDORID , MISCREG_ARCHID ,   MISCREG_IMPID , MISCREG_HARTID , MISCREG_STATUS , MISCREG_IP ,   MISCREG_IE , MISCREG_CYCLE , MISCREG_TIME , MISCREG_INSTRET ,   MISCREG_HPMCOUNTER03 , MISCREG_HPMCOUNTER04 , MISCREG_HPMCOUNTER05 , MISCREG_HPMCOUNTER06 ,   MISCREG_HPMCOUNTER07 , MISCREG_HPMCOUNTER08 , MISCREG_HPMCOUNTER09 , MISCREG_HPMCOUNTER10 ,   MISCREG_HPMCOUNTER11 , MISCREG_HPMCOUNTER12 , MISCREG_HPMCOUNTER13 , MISCREG_HPMCOUNTER14 ,   MISCREG_HPMCOUNTER15 , MISCREG_HPMCOUNTER16 , MISCREG_HPMCOUNTER17 , MISCREG_HPMCOUNTER18 ,   MISCREG_HPMCOUNTER19 , MISCREG_HPMCOUNTER20 , MISCREG_HPMCOUNTER21 , MISCREG_HPMCOUNTER22 ,   MISCREG_HPMCOUNTER23 , MISCREG_HPMCOUNTER24 , MISCREG_HPMCOUNTER25 , MISCREG_HPMCOUNTER26 ,   MISCREG_HPMCOUNTER27 , MISCREG_HPMCOUNTER28 , MISCREG_HPMCOUNTER29 , MISCREG_HPMCOUNTER30 ,   MISCREG_HPMCOUNTER31 , MISCREG_HPMEVENT03 , MISCREG_HPMEVENT04 , MISCREG_HPMEVENT05 ,   MISCREG_HPMEVENT06 , MISCREG_HPMEVENT07 , MISCREG_HPMEVENT08 , MISCREG_HPMEVENT09 ,   MISCREG_HPMEVENT10 , MISCREG_HPMEVENT11 , MISCREG_HPMEVENT12 , MISCREG_HPMEVENT13 ,   MISCREG_HPMEVENT14 , MISCREG_HPMEVENT15 , MISCREG_HPMEVENT16 , MISCREG_HPMEVENT17 ,   MISCREG_HPMEVENT18 , MISCREG_HPMEVENT19 , MISCREG_HPMEVENT20 , MISCREG_HPMEVENT21 ,   MISCREG_HPMEVENT22 , MISCREG_HPMEVENT23 , MISCREG_HPMEVENT24 , MISCREG_HPMEVENT25 ,   MISCREG_HPMEVENT26 , MISCREG_HPMEVENT27 , MISCREG_HPMEVENT28 , MISCREG_HPMEVENT29 ,   MISCREG_HPMEVENT30 , MISCREG_HPMEVENT31 , MISCREG_TSELECT , MISCREG_TDATA1 ,   MISCREG_TDATA2 , MISCREG_TDATA3 , MISCREG_DCSR , MISCREG_DPC ,   MISCREG_DSCRATCH , MISCREG_MEDELEG , MISCREG_MIDELEG , MISCREG_MTVEC ,   MISCREG_MCOUNTEREN , MISCREG_MSCRATCH , MISCREG_MEPC , MISCREG_MCAUSE ,   MISCREG_MTVAL , MISCREG_PMPCFG0 , MISCREG_PMPCFG1 , MISCREG_PMPCFG2 ,   MISCREG_PMPCFG3 , MISCREG_PMPADDR00 , MISCREG_PMPADDR01 , MISCREG_PMPADDR02 ,   MISCREG_PMPADDR03 , MISCREG_PMPADDR04 , MISCREG_PMPADDR05 , MISCREG_PMPADDR06 ,   MISCREG_PMPADDR07 , MISCREG_PMPADDR08 , MISCREG_PMPADDR09 , MISCREG_PMPADDR10 ,   MISCREG_PMPADDR11 , MISCREG_PMPADDR12 , MISCREG_PMPADDR13 , MISCREG_PMPADDR14 ,   MISCREG_PMPADDR15 , MISCREG_RESERVED01 , MISCREG_RESERVED02 , MISCREG_STVEC ,   MISCREG_SCOUNTEREN , MISCREG_SSCRATCH , MISCREG_SEPC , MISCREG_SCAUSE ,   MISCREG_STVAL , MISCREG_SATP , MISCREG_SENVCFG , MISCREG_RESERVED03 ,   MISCREG_RESERVED04 , MISCREG_RESERVED05 , MISCREG_RESERVED06 , MISCREG_RESERVED07 ,   MISCREG_FFLAGS , MISCREG_FRM , MISCREG_VSTART , MISCREG_VXSAT ,   MISCREG_VXRM , MISCREG_VCSR , MISCREG_VL , MISCREG_VTYPE ,   MISCREG_VLENB , MISCREG_HVIP , MISCREG_MTINST , MISCREG_MTVAL2 ,   MISCREG_HSTATUS , MISCREG_HEDELEG , MISCREG_HIDELEG , MISCREG_HCOUNTEREN ,   MISCREG_HGEIE , MISCREG_HTVAL , MISCREG_HTINST , MISCREG_HGEIP ,   MISCREG_HENVCFG , MISCREG_HGATP , MISCREG_HCONTEXT , MISCREG_HTIMEDELTA ,   MISCREG_VSSTATUS , MISCREG_VSTVEC , MISCREG_VSSCRATCH , MISCREG_VSEPC ,   MISCREG_VSCAUSE , MISCREG_VSTVAL , MISCREG_VSATP , MISCREG_VIRT ,   MISCREG_NMIVEC , MISCREG_NMIE , MISCREG_NMIP , MISCREG_MNSCRATCH ,   MISCREG_MNEPC , MISCREG_MNCAUSE , MISCREG_MNSTATUS , MISCREG_MSTATUSH ,   MISCREG_CYCLEH , MISCREG_TIMEH , MISCREG_INSTRETH , MISCREG_HPMCOUNTER03H ,   MISCREG_HPMCOUNTER04H , MISCREG_HPMCOUNTER05H , MISCREG_HPMCOUNTER06H , MISCREG_HPMCOUNTER07H ,   MISCREG_HPMCOUNTER08H , MISCREG_HPMCOUNTER09H , MISCREG_HPMCOUNTER10H , MISCREG_HPMCOUNTER11H ,   MISCREG_HPMCOUNTER12H , MISCREG_HPMCOUNTER13H , MISCREG_HPMCOUNTER14H , MISCREG_HPMCOUNTER15H ,   MISCREG_HPMCOUNTER16H , MISCREG_HPMCOUNTER17H , MISCREG_HPMCOUNTER18H , MISCREG_HPMCOUNTER19H ,   MISCREG_HPMCOUNTER20H , MISCREG_HPMCOUNTER21H , MISCREG_HPMCOUNTER22H , MISCREG_HPMCOUNTER23H ,   MISCREG_HPMCOUNTER24H , MISCREG_HPMCOUNTER25H , MISCREG_HPMCOUNTER26H , MISCREG_HPMCOUNTER27H ,   MISCREG_HPMCOUNTER28H , MISCREG_HPMCOUNTER29H , MISCREG_HPMCOUNTER30H , MISCREG_HPMCOUNTER31H ,   MISCREG_JVT , NUM_PHYS_MISCREGS , MISCREG_FFLAGS_EXE = NUM_PHYS_MISCREGS , NUM_MISCREGS }
enum	CSRIndex {   CSR_FFLAGS = 0x001 , CSR_FRM = 0x002 , CSR_FCSR = 0x003 , CSR_CYCLE = 0xC00 ,   CSR_TIME = 0xC01 , CSR_INSTRET = 0xC02 , CSR_HPMCOUNTER03 = 0xC03 , CSR_HPMCOUNTER04 = 0xC04 ,   CSR_HPMCOUNTER05 = 0xC05 , CSR_HPMCOUNTER06 = 0xC06 , CSR_HPMCOUNTER07 = 0xC07 , CSR_HPMCOUNTER08 = 0xC08 ,   CSR_HPMCOUNTER09 = 0xC09 , CSR_HPMCOUNTER10 = 0xC0A , CSR_HPMCOUNTER11 = 0xC0B , CSR_HPMCOUNTER12 = 0xC0C ,   CSR_HPMCOUNTER13 = 0xC0D , CSR_HPMCOUNTER14 = 0xC0E , CSR_HPMCOUNTER15 = 0xC0F , CSR_HPMCOUNTER16 = 0xC10 ,   CSR_HPMCOUNTER17 = 0xC11 , CSR_HPMCOUNTER18 = 0xC12 , CSR_HPMCOUNTER19 = 0xC13 , CSR_HPMCOUNTER20 = 0xC14 ,   CSR_HPMCOUNTER21 = 0xC15 , CSR_HPMCOUNTER22 = 0xC16 , CSR_HPMCOUNTER23 = 0xC17 , CSR_HPMCOUNTER24 = 0xC18 ,   CSR_HPMCOUNTER25 = 0xC19 , CSR_HPMCOUNTER26 = 0xC1A , CSR_HPMCOUNTER27 = 0xC1B , CSR_HPMCOUNTER28 = 0xC1C ,   CSR_HPMCOUNTER29 = 0xC1D , CSR_HPMCOUNTER30 = 0xC1E , CSR_HPMCOUNTER31 = 0xC1F , CSR_CYCLEH = 0xC80 ,   CSR_TIMEH = 0xC81 , CSR_INSTRETH = 0xC82 , CSR_HPMCOUNTER03H = 0xC83 , CSR_HPMCOUNTER04H = 0xC84 ,   CSR_HPMCOUNTER05H = 0xC85 , CSR_HPMCOUNTER06H = 0xC86 , CSR_HPMCOUNTER07H = 0xC87 , CSR_HPMCOUNTER08H = 0xC88 ,   CSR_HPMCOUNTER09H = 0xC89 , CSR_HPMCOUNTER10H = 0xC8A , CSR_HPMCOUNTER11H = 0xC8B , CSR_HPMCOUNTER12H = 0xC8C ,   CSR_HPMCOUNTER13H = 0xC8D , CSR_HPMCOUNTER14H = 0xC8E , CSR_HPMCOUNTER15H = 0xC8F , CSR_HPMCOUNTER16H = 0xC90 ,   CSR_HPMCOUNTER17H = 0xC91 , CSR_HPMCOUNTER18H = 0xC92 , CSR_HPMCOUNTER19H = 0xC93 , CSR_HPMCOUNTER20H = 0xC94 ,   CSR_HPMCOUNTER21H = 0xC95 , CSR_HPMCOUNTER22H = 0xC96 , CSR_HPMCOUNTER23H = 0xC97 , CSR_HPMCOUNTER24H = 0xC98 ,   CSR_HPMCOUNTER25H = 0xC99 , CSR_HPMCOUNTER26H = 0xC9A , CSR_HPMCOUNTER27H = 0xC9B , CSR_HPMCOUNTER28H = 0xC9C ,   CSR_HPMCOUNTER29H = 0xC9D , CSR_HPMCOUNTER30H = 0xC9E , CSR_HPMCOUNTER31H = 0xC9F , CSR_SSTATUS = 0x100 ,   CSR_SIE = 0x104 , CSR_STVEC = 0x105 , CSR_SCOUNTEREN = 0x106 , CSR_SSCRATCH = 0x140 ,   CSR_SEPC = 0x141 , CSR_SCAUSE = 0x142 , CSR_STVAL = 0x143 , CSR_SIP = 0x144 ,   CSR_SATP = 0x180 , CSR_SENVCFG = 0x10A , CSR_MVENDORID = 0xF11 , CSR_MARCHID = 0xF12 ,   CSR_MIMPID = 0xF13 , CSR_MHARTID = 0xF14 , CSR_MSTATUS = 0x300 , CSR_MISA = 0x301 ,   CSR_MEDELEG = 0x302 , CSR_MIDELEG = 0x303 , CSR_MIE = 0x304 , CSR_MTVEC = 0x305 ,   CSR_MCOUNTEREN = 0x306 , CSR_MSTATUSH = 0x310 , CSR_MSCRATCH = 0x340 , CSR_MEPC = 0x341 ,   CSR_MCAUSE = 0x342 , CSR_MTVAL = 0x343 , CSR_MIP = 0x344 , CSR_PMPCFG0 = 0x3A0 ,   CSR_PMPCFG1 = 0x3A1 , CSR_PMPCFG2 = 0x3A2 , CSR_PMPCFG3 = 0x3A3 , CSR_PMPADDR00 = 0x3B0 ,   CSR_PMPADDR01 = 0x3B1 , CSR_PMPADDR02 = 0x3B2 , CSR_PMPADDR03 = 0x3B3 , CSR_PMPADDR04 = 0x3B4 ,   CSR_PMPADDR05 = 0x3B5 , CSR_PMPADDR06 = 0x3B6 , CSR_PMPADDR07 = 0x3B7 , CSR_PMPADDR08 = 0x3B8 ,   CSR_PMPADDR09 = 0x3B9 , CSR_PMPADDR10 = 0x3BA , CSR_PMPADDR11 = 0x3BB , CSR_PMPADDR12 = 0x3BC ,   CSR_PMPADDR13 = 0x3BD , CSR_PMPADDR14 = 0x3BE , CSR_PMPADDR15 = 0x3BF , CSR_MCYCLE = 0xB00 ,   CSR_MINSTRET = 0xB02 , CSR_MHPMCOUNTER03 = 0xB03 , CSR_MHPMCOUNTER04 = 0xB04 , CSR_MHPMCOUNTER05 = 0xB05 ,   CSR_MHPMCOUNTER06 = 0xB06 , CSR_MHPMCOUNTER07 = 0xB07 , CSR_MHPMCOUNTER08 = 0xB08 , CSR_MHPMCOUNTER09 = 0xB09 ,   CSR_MHPMCOUNTER10 = 0xB0A , CSR_MHPMCOUNTER11 = 0xB0B , CSR_MHPMCOUNTER12 = 0xB0C , CSR_MHPMCOUNTER13 = 0xB0D ,   CSR_MHPMCOUNTER14 = 0xB0E , CSR_MHPMCOUNTER15 = 0xB0F , CSR_MHPMCOUNTER16 = 0xB10 , CSR_MHPMCOUNTER17 = 0xB11 ,   CSR_MHPMCOUNTER18 = 0xB12 , CSR_MHPMCOUNTER19 = 0xB13 , CSR_MHPMCOUNTER20 = 0xB14 , CSR_MHPMCOUNTER21 = 0xB15 ,   CSR_MHPMCOUNTER22 = 0xB16 , CSR_MHPMCOUNTER23 = 0xB17 , CSR_MHPMCOUNTER24 = 0xB18 , CSR_MHPMCOUNTER25 = 0xB19 ,   CSR_MHPMCOUNTER26 = 0xB1A , CSR_MHPMCOUNTER27 = 0xB1B , CSR_MHPMCOUNTER28 = 0xB1C , CSR_MHPMCOUNTER29 = 0xB1D ,   CSR_MHPMCOUNTER30 = 0xB1E , CSR_MHPMCOUNTER31 = 0xB1F , CSR_MCYCLEH = 0xB80 , CSR_MINSTRETH = 0xB82 ,   CSR_MHPMCOUNTER03H = 0xB83 , CSR_MHPMCOUNTER04H = 0xB84 , CSR_MHPMCOUNTER05H = 0xB85 , CSR_MHPMCOUNTER06H = 0xB86 ,   CSR_MHPMCOUNTER07H = 0xB87 , CSR_MHPMCOUNTER08H = 0xB88 , CSR_MHPMCOUNTER09H = 0xB89 , CSR_MHPMCOUNTER10H = 0xB8A ,   CSR_MHPMCOUNTER11H = 0xB8B , CSR_MHPMCOUNTER12H = 0xB8C , CSR_MHPMCOUNTER13H = 0xB8D , CSR_MHPMCOUNTER14H = 0xB8E ,   CSR_MHPMCOUNTER15H = 0xB8F , CSR_MHPMCOUNTER16H = 0xB90 , CSR_MHPMCOUNTER17H = 0xB91 , CSR_MHPMCOUNTER18H = 0xB92 ,   CSR_MHPMCOUNTER19H = 0xB93 , CSR_MHPMCOUNTER20H = 0xB94 , CSR_MHPMCOUNTER21H = 0xB95 , CSR_MHPMCOUNTER22H = 0xB96 ,   CSR_MHPMCOUNTER23H = 0xB97 , CSR_MHPMCOUNTER24H = 0xB98 , CSR_MHPMCOUNTER25H = 0xB99 , CSR_MHPMCOUNTER26H = 0xB9A ,   CSR_MHPMCOUNTER27H = 0xB9B , CSR_MHPMCOUNTER28H = 0xB9C , CSR_MHPMCOUNTER29H = 0xB9D , CSR_MHPMCOUNTER30H = 0xB9E ,   CSR_MHPMCOUNTER31H = 0xB9F , CSR_MHPMEVENT03 = 0x323 , CSR_MHPMEVENT04 = 0x324 , CSR_MHPMEVENT05 = 0x325 ,   CSR_MHPMEVENT06 = 0x326 , CSR_MHPMEVENT07 = 0x327 , CSR_MHPMEVENT08 = 0x328 , CSR_MHPMEVENT09 = 0x329 ,   CSR_MHPMEVENT10 = 0x32A , CSR_MHPMEVENT11 = 0x32B , CSR_MHPMEVENT12 = 0x32C , CSR_MHPMEVENT13 = 0x32D ,   CSR_MHPMEVENT14 = 0x32E , CSR_MHPMEVENT15 = 0x32F , CSR_MHPMEVENT16 = 0x330 , CSR_MHPMEVENT17 = 0x331 ,   CSR_MHPMEVENT18 = 0x332 , CSR_MHPMEVENT19 = 0x333 , CSR_MHPMEVENT20 = 0x334 , CSR_MHPMEVENT21 = 0x335 ,   CSR_MHPMEVENT22 = 0x336 , CSR_MHPMEVENT23 = 0x337 , CSR_MHPMEVENT24 = 0x338 , CSR_MHPMEVENT25 = 0x339 ,   CSR_MHPMEVENT26 = 0x33A , CSR_MHPMEVENT27 = 0x33B , CSR_MHPMEVENT28 = 0x33C , CSR_MHPMEVENT29 = 0x33D ,   CSR_MHPMEVENT30 = 0x33E , CSR_MHPMEVENT31 = 0x33F , CSR_TSELECT = 0x7A0 , CSR_TDATA1 = 0x7A1 ,   CSR_TDATA2 = 0x7A2 , CSR_TDATA3 = 0x7A3 , CSR_DCSR = 0x7B0 , CSR_DPC = 0x7B1 ,   CSR_DSCRATCH = 0x7B2 , CSR_VSTART = 0x008 , CSR_VXSAT = 0x009 , CSR_VXRM = 0x00A ,   CSR_VCSR = 0x00F , CSR_VL = 0xC20 , CSR_VTYPE = 0xC21 , CSR_VLENB = 0xC22 ,   CSR_MNSCRATCH = 0x740 , CSR_MNEPC = 0x741 , CSR_MNCAUSE = 0x742 , CSR_MNSTATUS = 0x744 ,   CSR_JVT = 0x017 , CSR_MTINST = 0x34A , CSR_MTVAL2 = 0x34B , CSR_HSTATUS = 0x600 ,   CSR_HEDELEG = 0x602 , CSR_HIDELEG = 0x603 , CSR_HIE = 0x604 , CSR_HTIMEDELTA = 0x605 ,   CSR_HCOUNTEREN = 0x606 , CSR_HGEIE = 0x607 , CSR_HTVAL = 0x643 , CSR_HIP = 0x644 ,   CSR_HVIP = 0x645 , CSR_HTINST = 0x64A , CSR_HGEIP = 0xE12 , CSR_HENVCFG = 0x60A ,   CSR_HGATP = 0x680 , CSR_HCONTEXT = 0x6A8 , CSR_VSSTATUS = 0x200 , CSR_VSIE = 0x204 ,   CSR_VSTVEC = 0x205 , CSR_VSSCRATCH = 0x240 , CSR_VSEPC = 0x241 , CSR_VSCAUSE = 0x242 ,   CSR_VSTVAL = 0x243 , CSR_VSIP = 0x244 , CSR_VSATP = 0x280 }
enum	XlateStage { FIRST_STAGE , GSTAGE }

Functions
bool	getFaultVAddr (Fault fault, Addr &va)
	Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.
float	getVflmul (uint32_t vlmul_encoding)
	This function translates the 3-bit value of vlmul bits to the corresponding lmul value as specified in RVV 1.0 spec p11-12 chapter 3.4.2.
uint32_t	getVlmax (VTYPE vtype, uint32_t vlen)
uint32_t	getSew (uint32_t vsew)
uint32_t	get_emul (uint32_t eew, uint32_t sew, float vflmul, bool is_mask_ldst)
uint8_t	checked_vtype (bool vill, uint8_t vtype)
bool	virtualizationEnabled (ExecContext *xc)
bool	virtualizationEnabled (ThreadContext *tc)
void	setV (ExecContext *xc)
void	setV (ThreadContext *tc)
void	resetV (ExecContext *xc)
void	resetV (ThreadContext *tc)
Fault	updateFPUStatus (ExecContext *xc, ExtMachInst machInst, bool set_dirty)
Fault	updateVPUStatus (ExecContext *xc, ExtMachInst machInst, bool set_dirty, bool check_vill)
static SyscallReturn	unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler.
static SyscallReturn	unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler.
static void	cpumask_set_cpu (unsigned int cpu, RiscvLinux::cpumask_t *dstp)
static void	cpumask_clear_cpu (unsigned int cpu, RiscvLinux::cpumask_t *dstp)
static bool	cpumask_test_cpu (unsigned int cpu, const RiscvLinux::cpumask_t *cpumask)
static void	cpumask_and (RiscvLinux::cpumask_t *dstp, const RiscvLinux::cpumask_t *src1p, const RiscvLinux::cpumask_t *src2p)
static bool	cpumask_empty (const RiscvLinux::cpumask_t *dstp)
static void	cpumask_copy (RiscvLinux::cpumask_t *dstp, const RiscvLinux::cpumask_t *srcp)
static void	cpumask_clear (RiscvLinux::cpumask_t *dstp)
static RiscvLinux::cpumask_t *	cpumask_malloc (ThreadContext *tc)
static void	cpumask_free (RiscvLinux::cpumask_t *cpu_online_mask)
static bool	riscv_hwprobe_key_is_valid (int64_t key)
static bool	hwprobe_key_is_bitmask (int64_t key)
static bool	riscv_hwprobe_pair_cmp (RiscvLinux::riscv_hwprobe *pair, RiscvLinux::riscv_hwprobe *other_pair)
static RiscvLinux::cpumask_t *	get_cpu_online_mask (ThreadContext *tc)
static void	hwprobe_one_pair (ThreadContext *tc, RiscvLinux::riscv_hwprobe *pair, RiscvLinux::cpumask_t *cpus)
template<class OS>
static int	hwprobe_get_values (ThreadContext *tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags)
template<class OS>
static int	hwprobe_get_cpus (ThreadContext *tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags)
template<class OS>
static SyscallReturn	riscvHWProbeFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags)
Addr	getVPNFromVAddr (Addr vaddr, Addr mode)
	BitUnion64 (SATP) Bitfield< 63
	EndBitUnion (SATP) enum AddrXlateMode
	BitUnion64 (PTESv39) Bitfield< 63 > n
	EndBitUnion (PTESv39) Addr getVPNFromVAddr(Addr vaddr
	Remove the page offset and the upper bits that are not part of the VPN from the address.
	BitUnion32 (IndexReg) Bitfield< 31 > p
	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
	EndSubBitUnion (cu) Bitfield< 27 > rp
	SubBitUnion (im, 15, 8) Bitfield< 15 > im7
	EndSubBitUnion (im) Bitfield< 7 > kx
	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
	EndSubBitUnion (ip)
	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
static constexpr uint16_t	unboxF16 (uint64_t v)
static constexpr uint32_t	unboxF32 (uint64_t v)
static constexpr uint64_t	boxF16 (uint16_t v)
static constexpr uint64_t	boxF32 (uint32_t v)
static constexpr float16_t	f16 (uint16_t v)
static constexpr float32_t	f32 (uint32_t v)
static constexpr float64_t	f64 (uint64_t v)
static constexpr float16_t	f16 (freg_t r)
static constexpr float32_t	f32 (freg_t r)
static constexpr float64_t	f64 (freg_t r)
static constexpr freg_t	freg (float16_t f)
static constexpr freg_t	freg (float32_t f)
static constexpr freg_t	freg (float64_t f)
static constexpr freg_t	freg (uint_fast64_t f)
constexpr RegClass	floatRegClass (FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
float16_t	fsgnj16 (float16_t a, float16_t b, bool n, bool x)
float32_t	fsgnj32 (float32_t a, float32_t b, bool n, bool x)
float64_t	fsgnj64 (float64_t a, float64_t b, bool n, bool x)
constexpr RegClass	intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
constexpr RegClass	miscRegClass (MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)
template<typename... T>
constexpr uint64_t	rvTypeFlags (T... args)
template<typename... T>
constexpr uint64_t	isaExtsFlags (T... isa_exts)
constexpr uint64_t	isaExtsFlags ()
	BitUnion64 (STATUS) Bitfield< 63 > rv64_sd
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.
	EndBitUnion (STATUS) BitUnion64(HSTATUS) Bitfield< 33
	EndBitUnion (HSTATUS) BitUnion64(NSTATUS) Bitfield< 12
	These fields are specified in the RISC-V Instruction Set Manual.
	EndBitUnion (NSTATUS) BitUnion64(MISA) Bitfield< 63
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org.
	EndBitUnion (MISA) BitUnion64(INTERRUPT) Bitfield< 63
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.
	EndBitUnion (INTERRUPT) BitUnion64(SENVCFG) Bitfield< 63
	EndBitUnion (SENVCFG) BitUnion64(JVT) Bitfield< 63
	EndBitUnion (JVT) const off_t MXL_OFFSETS[enums
	BitUnion64 (VTYPE) Bitfield< 63 > vill
int32_t	_rvk_emu_sll_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_srl_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_sll_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_srl_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_rol_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_ror_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_rol_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_ror_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_grev_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_grev_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_brev8_32 (int32_t rs1)
int64_t	_rvk_emu_brev8_64 (int64_t rs1)
uint32_t	_rvk_emu_shuffle32_stage (uint32_t src, uint32_t maskL, uint32_t maskR, int N)
int32_t	_rvk_emu_shfl_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_unshfl_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_zip_32 (int32_t rs1)
int32_t	_rvk_emu_unzip_32 (int32_t rs1)
int32_t	_rvk_emu_clmul_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_clmulh_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_clmul_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_clmulh_64 (int64_t rs1, int64_t rs2)
uint32_t	_rvk_emu_xperm32 (uint32_t rs1, uint32_t rs2, int sz_log2)
int32_t	_rvk_emu_xperm4_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_xperm8_32 (int32_t rs1, int32_t rs2)
uint64_t	_rvk_emu_xperm64 (uint64_t rs1, uint64_t rs2, int sz_log2)
int64_t	_rvk_emu_xperm4_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_xperm8_64 (int64_t rs1, int64_t rs2)
uint8_t	_rvk_emu_aes_xtime (uint8_t x)
uint32_t	_rvk_emu_aes_fwd_mc_8 (uint32_t x)
uint32_t	_rvk_emu_aes_fwd_mc_32 (uint32_t x)
uint32_t	_rvk_emu_aes_inv_mc_8 (uint32_t x)
uint32_t	_rvk_emu_aes_inv_mc_32 (uint32_t x)
int32_t	_rvk_emu_aes32dsi (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_aes32dsmi (int32_t rs1, int32_t rs2, uint8_t bs)
int64_t	_rvk_emu_aes64ds (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64im (int64_t rs1)
int64_t	_rvk_emu_aes64dsm (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64ks1i (int64_t rs1, int rnum)
int64_t	_rvk_emu_aes64ks2 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_aes32esi (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_aes32esmi (int32_t rs1, int32_t rs2, uint8_t bs)
int64_t	_rvk_emu_aes64es (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64esm (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_sha256sig0 (int32_t rs1)
int32_t	_rvk_emu_sha256sig1 (int32_t rs1)
int32_t	_rvk_emu_sha256sum0 (int32_t rs1)
int32_t	_rvk_emu_sha256sum1 (int32_t rs1)
static int32_t	_rvk_emu_sha512sig0h (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig0l (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig1h (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig1l (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sum0r (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sum1r (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_sha512sig0 (int64_t rs1)
int64_t	_rvk_emu_sha512sig1 (int64_t rs1)
int64_t	_rvk_emu_sha512sum0 (int64_t rs1)
int64_t	_rvk_emu_sha512sum1 (int64_t rs1)
int32_t	_rvk_emu_sm4ed (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_sm4ks (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_sm3p0 (int32_t rs1)
int32_t	_rvk_emu_sm3p1 (int32_t rs1)
	BitUnion64 (ExtMachInst) Bitfield< 63
	SubBitUnion (vtype8, 39, 32) Bitfield< 39 > vma
	EndSubBitUnion (vtype8) uint32_t instBits
	EndBitUnion (ExtMachInst) const expr unsigned MaxVecLenInBits
template<typename T>
bool	isquietnan (T val)
template<>
bool	isquietnan< float > (float val)
template<>
bool	isquietnan< double > (double val)
template<typename T>
bool	issignalingnan (T val)
template<>
bool	issignalingnan< float > (float val)
template<>
bool	issignalingnan< double > (double val)
std::string	registerName (RegId reg)
template<typename T>
std::make_unsigned_t< T >	mulhu (std::make_unsigned_t< T > rs1, std::make_unsigned_t< T > rs2)
template<typename T>
std::make_signed_t< T >	mulh (std::make_signed_t< T > rs1, std::make_signed_t< T > rs2)
template<typename T>
std::make_signed_t< T >	mulhsu (std::make_signed_t< T > rs1, std::make_unsigned_t< T > rs2)
template<typename T>
T	div (T rs1, T rs2)
template<typename T>
T	divu (T rs1, T rs2)
template<typename T>
T	rem (T rs1, T rs2)
template<typename T>
T	remu (T rs1, T rs2)
uint64_t	vtype_SEW (const uint64_t vtype)
uint64_t	vtype_VLMAX (const uint64_t vtype, const uint64_t vlen, const bool per_reg=false)
int64_t	vtype_vlmul (const uint64_t vtype)
uint64_t	vtype_regs_per_group (const uint64_t vtype)
void	vtype_set_vill (uint64_t &vtype)
uint64_t	width_EEW (uint64_t width)
template<typename T>
int	elem_mask (const T *vs, const int index)
template<typename T>
int	elem_mask_vseg (const T *vs, const int elem, const int num_fields)
template<typename FloatType, typename IntType = decltype(FloatType::v)>
auto	ftype (IntType a) -> FloatType
template<typename FloatType, typename IntType = decltype(FloatType::v)>
auto	ftype_freg (freg_t a) -> FloatType
template<typename FloatType>
FloatType	fadd (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fsub (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fmin (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fmax (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fdiv (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fmul (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fsqrt (FloatType a)
template<typename FloatType>
FloatType	frsqrte7 (FloatType a)
template<typename FloatType>
FloatType	frecip7 (FloatType a)
template<typename FloatType>
FloatType	fclassify (FloatType a)
template<typename FloatType>
FloatType	fsgnj (FloatType a, FloatType b, bool n, bool x)
template<typename FloatType>
bool	fle (FloatType a, FloatType b)
template<typename FloatType>
bool	feq (FloatType a, FloatType b)
template<typename FloatType>
bool	flt (FloatType a, FloatType b)
template<typename FloatType>
FloatType	fmadd (FloatType a, FloatType b, FloatType c)
template<typename FloatType>
FloatType	fneg (FloatType a)
template<typename FT, typename WFT = typename double_width<FT>::type>
WFT	fwiden (FT a)
template<typename FloatType, typename IntType = decltype(FloatType::v)>
IntType	f_to_ui (FloatType a, uint_fast8_t mode)
template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>
IntType	f_to_wui (FloatType a, uint_fast8_t mode)
template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>
IntType	f_to_nui (FloatType a, uint_fast8_t mode)
template<typename FloatType, typename IntType = decltype(FloatType::v)>
IntType	f_to_i (FloatType a, uint_fast8_t mode)
template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>
IntType	f_to_wi (FloatType a, uint_fast8_t mode)
template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>
IntType	f_to_ni (FloatType a, uint_fast8_t mode)
template<typename FloatType, typename IntType = decltype(FloatType::v)>
FloatType	ui_to_f (IntType a)
template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>
FloatType	ui_to_wf (IntType a)
template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>
FloatType	ui_to_nf (IntType a)
template<typename FloatType, typename IntType = decltype(FloatType::v)>
FloatType	i_to_f (IntType a)
template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>
FloatType	i_to_wf (IntType a)
template<typename FloatType, typename IntType = std::make_signed_t< decltype(double_width<FloatType>::type::v) >>
FloatType	i_to_nf (IntType a)
template<typename FloatType, typename FloatWType = typename double_width<FloatType>::type>
FloatWType	f_to_wf (FloatType a)
template<typename FloatNType, typename FloatType = typename double_width<FloatNType>::type>
FloatNType	f_to_nf (FloatType a)
template<typename T>
T	sat_add (T x, T y, bool *sat)
template<typename T>
T	sat_sub (T x, T y, bool *sat)
template<typename T>
T	sat_addu (T x, T y, bool *sat)
template<typename T>
T	sat_subu (T x, T y, bool *sat)
template<typename T>
T	int_rounding (T result, uint8_t xrm, unsigned gb)
	Ref: https://github.com/riscv-software-src/riscv-isa-sim.

Variables
const RegVal	DELEGABLE_EXCPS
const RegVal	DELEGABLE_EXCPS_WITH_RVH
const RegVal	VS_DELEGABLE_EXCPS
const std::array< const char *, NUM_MISCREGS >	MiscRegNames
const Addr	PageShift = 12
const Addr	PageBytes = 1ULL << PageShift
const Addr	NapotShift = 4
	mode
Bitfield< 59, 44 >	asid
Bitfield< 43, 0 >	ppn
const Addr	SV39_XLEN = 64
const Addr	SV39_VADDR_BITS = 39
const Addr	SV39_LEVELS = 3
const Addr	SV39_LEVEL_BITS = 9
const Addr	SV39X4_WIDENED_BITS = 2
Bitfield< 62, 54 >	reserved
Bitfield< 53, 28 >	ppn2
Bitfield< 27, 19 >	ppn1
Bitfield< 18, 10 >	ppn0
Bitfield< 7 >	d
Bitfield< 6 >	a
Bitfield< 5 >	g
Bitfield< 4 >	u
Bitfield< 3, 1 >	perm
Bitfield< 3 >	x
Bitfield< 2 >	w
Bitfield< 1 >	r
Bitfield< 0 >	v
constexpr enums::RiscvType	RV32 = enums::RV32
constexpr enums::RiscvType	RV64 = enums::RV64
Bitfield< 30, 0 >	index
	random
	fill
Bitfield< 29, 6 >	pfn
Bitfield< 5, 3 >	c
	pteBase
Bitfield< 22, 4 >	badVPN2
	mask
Bitfield< 12, 11 >	maskx
	aseUp
Bitfield< 29 >	elpa
Bitfield< 28 >	esp
Bitfield< 12, 8 >	aseDn
	wired
	impl
Bitfield< 39, 13 >	vpn2
Bitfield< 12, 11 >	vpn2x
Bitfield< 31 >	cu3
Bitfield< 30 >	cu2
Bitfield< 29 >	cu1
Bitfield< 28 >	cu0
Bitfield< 26 >	fr
Bitfield< 25 >	re
Bitfield< 24 >	mx
Bitfield< 23 >	px
Bitfield< 22 >	bev
Bitfield< 21 >	ts
Bitfield< 20 >	sr
Bitfield< 19 >	nmi
Bitfield< 15, 10 >	ipl
Bitfield< 14 >	im6
Bitfield< 13 >	im5
Bitfield< 12 >	im4
Bitfield< 11 >	im3
Bitfield< 10 >	im2
Bitfield< 9 >	im1
Bitfield< 8 >	im0
Bitfield< 6 >	sx
Bitfield< 5 >	ux
Bitfield< 4, 3 >	ksu
Bitfield< 4 >	um
Bitfield< 3 >	r0
Bitfield< 2 >	erl
Bitfield< 1 >	exl
Bitfield< 0 >	ie
	ipti
Bitfield< 28, 26 >	ippci
Bitfield< 9, 5 >	vs
	hss
Bitfield< 21, 18 >	eicss
Bitfield< 15, 12 >	ess
Bitfield< 9, 6 >	pss
Bitfield< 3, 0 >	css
	ssv7
Bitfield< 27, 24 >	ssv6
Bitfield< 23, 20 >	ssv5
Bitfield< 19, 16 >	ssv4
Bitfield< 15, 12 >	ssv3
Bitfield< 11, 8 >	ssv2
Bitfield< 7, 4 >	ssv1
Bitfield< 3, 0 >	ssv0
Bitfield< 30 >	ti
Bitfield< 29, 28 >	ce
Bitfield< 27 >	dc
Bitfield< 26 >	pci
Bitfield< 23 >	iv
Bitfield< 22 >	wp
Bitfield< 15, 10 >	ripl
Bitfield< 14 >	ip6
Bitfield< 13 >	ip5
Bitfield< 12 >	ip4
Bitfield< 11 >	ip3
Bitfield< 10 >	ip2
Bitfield< 9 >	ip1
Bitfield< 8 >	ip0
Bitfield< 6, 2 >	excCode
	coOp
Bitfield< 23, 16 >	coId
Bitfield< 15, 8 >	procId
Bitfield< 7, 0 >	rev
	exceptionBase
Bitfield< 9, 9 >	cpuNum
Bitfield< 30, 28 >	k23
Bitfield< 27, 25 >	ku
Bitfield< 15 >	be
Bitfield< 14, 13 >	at
Bitfield< 12, 10 >	ar
Bitfield< 9, 7 >	mt
Bitfield< 3 >	vi
Bitfield< 2, 0 >	k0
Bitfield< 30, 25 >	mmuSize
Bitfield< 24, 22 >	is
Bitfield< 21, 19 >	il
Bitfield< 18, 16 >	ia
Bitfield< 15, 13 >	ds
Bitfield< 12, 10 >	dl
Bitfield< 9, 7 >	da
Bitfield< 6 >	c2
Bitfield< 5 >	md
Bitfield< 4 >	pc
Bitfield< 3 >	wr
Bitfield< 2 >	ca
Bitfield< 1 >	ep
Bitfield< 0 >	fp
Bitfield< 30, 28 >	tu
Bitfield< 23, 20 >	tl
Bitfield< 19, 16 >	ta
Bitfield< 15, 12 >	su
Bitfield< 11, 8 >	ss
Bitfield< 7, 4 >	sl
Bitfield< 3, 0 >	sa
Bitfield< 10 >	dspp
Bitfield< 7 >	lpa
Bitfield< 6 >	veic
Bitfield< 5 >	vint
Bitfield< 4 >	sp
Bitfield< 1 >	sm
	vaddr
Bitfield< 2 >	i
Bitfield< 10, 5 >	event
Bitfield< 2 >	s
Bitfield< 1 >	k
Bitfield< 30 >	ec
Bitfield< 29 >	ed
Bitfield< 28 >	et
Bitfield< 27 >	es
Bitfield< 26 >	ee
Bitfield< 25 >	eb
	pTagLo
Bitfield< 7, 6 >	pState
Bitfield< 5 >	l
Bitfield< 0 >	p
constexpr auto &	ReturnAddrReg = int_reg::Ra
constexpr auto &	StackPointerReg = int_reg::Sp
constexpr auto &	ThreadPointerReg = int_reg::Tp
constexpr auto &	ReturnValueReg = int_reg::A0
constexpr auto &	AMOTempReg = int_reg::Ureg0
constexpr auto &	SyscallNumReg = int_reg::A7
constexpr RegId	ArgumentRegs []
const std::vector< RegId >	PushPopRegList
constexpr RegId	StackRegs []
const std::unordered_map< int, CSRMetadata >	CSRData
Bitfield< 39 >	mpv
Bitfield< 38 >	gva
Bitfield< 37 >	mbe
Bitfield< 36 >	sbe
Bitfield< 35, 34 >	sxl
Bitfield< 33, 32 >	uxl
Bitfield< 31 >	rv32_sd
Bitfield< 22 >	tsr
Bitfield< 21 >	tw
Bitfield< 20 >	tvm
Bitfield< 19 >	mxr
Bitfield< 18 >	sum
Bitfield< 17 >	mprv
Bitfield< 16, 15 >	xs
Bitfield< 14, 13 >	fs
Bitfield< 12, 11 >	mpp
Bitfield< 8 >	spp
Bitfield< 7 >	mpie
Bitfield< 6 >	ube
Bitfield< 5 >	spie
Bitfield< 3 >	mie
Bitfield< 1 >	sie
	vsxl
Bitfield< 22 >	vtsr
Bitfield< 21 >	vtw
Bitfield< 20 >	vtvm
Bitfield< 17, 12 >	vgein
Bitfield< 9 >	hu
Bitfield< 8 >	spvp
Bitfield< 7 >	spv
Bitfield< 5 >	vsbe
	mnpp
Bitfield< 7 >	mnv
Bitfield< 3 >	nmie
	rv64_mxl
Bitfield< 31, 30 >	rv32_mxl
Bitfield< 23 >	rvx
Bitfield< 21 >	rvv
Bitfield< 20 >	rvu
Bitfield< 19 >	rvt
Bitfield< 18 >	rvs
Bitfield< 16 >	rvq
Bitfield< 15 >	rvp
Bitfield< 13 >	rvn
Bitfield< 12 >	rvm
Bitfield< 11 >	rvl
Bitfield< 10 >	rvk
Bitfield< 9 >	rvj
Bitfield< 8 >	rvi
Bitfield< 7 >	rvh
Bitfield< 6 >	rvg
Bitfield< 5 >	rvf
Bitfield< 4 >	rve
Bitfield< 3 >	rvd
Bitfield< 2 >	rvc
Bitfield< 1 >	rvb
Bitfield< 0 >	rva
	local
Bitfield< 12 >	sgei
Bitfield< 11 >	mei
Bitfield< 10 >	vsei
Bitfield< 9 >	sei
Bitfield< 7 >	mti
Bitfield< 6 >	vsti
Bitfield< 5 >	sti
Bitfield< 3 >	msi
Bitfield< 2 >	vssi
Bitfield< 1 >	ssi
	wpri_1
Bitfield< 33, 32 >	pmm
Bitfield< 31, 8 >	wpri_2
Bitfield< 7 >	cbze
Bitfield< 6 >	cbcfe
Bitfield< 5, 4 >	cbie
Bitfield< 3, 1 >	wpri_3
Bitfield< 0 >	fiom
	base
const off_t	MBE_OFFSET [enums::Num_RiscvType]
const off_t	SBE_OFFSET [enums::Num_RiscvType]
const off_t	SXL_OFFSET = 34
const off_t	VSXL_OFFSET = 32
const off_t	UXL_OFFSET = 32
const off_t	FS_OFFSET = 13
const off_t	VS_OFFSET = 9
const off_t	FRM_OFFSET = 5
const RegVal	ISA_MXL_MASKS [enums::Num_RiscvType]
const RegVal	ISA_EXT_MASK = mask(26)
const RegVal	ISA_EXT_C_MASK = 1UL << ('c' - 'a')
const RegVal	MISA_MASKS [enums::Num_RiscvType]
const RegVal	STATUS_SD_MASKS [enums::Num_RiscvType]
const RegVal	STATUS_MBE_MASK [enums::Num_RiscvType]
const RegVal	STATUS_SBE_MASK [enums::Num_RiscvType]
const RegVal	STATUS_MPV_MASK = 1LL << 39
const RegVal	STATUS_GVA_MASK = 1LL << 38
const RegVal	STATUS_SXL_MASK = 3ULL << SXL_OFFSET
const RegVal	STATUS_UXL_MASK = 3ULL << UXL_OFFSET
const RegVal	STATUS_TSR_MASK = 1ULL << 22
const RegVal	STATUS_TW_MASK = 1ULL << 21
const RegVal	STATUS_TVM_MASK = 1ULL << 20
const RegVal	STATUS_MXR_MASK = 1ULL << 19
const RegVal	STATUS_SUM_MASK = 1ULL << 18
const RegVal	STATUS_MPRV_MASK = 1ULL << 17
const RegVal	STATUS_XS_MASK = 3ULL << 15
const RegVal	STATUS_FS_MASK = 3ULL << FS_OFFSET
const RegVal	STATUS_MPP_MASK = 3ULL << 11
const RegVal	STATUS_VS_MASK = 3ULL << VS_OFFSET
const RegVal	STATUS_SPP_MASK = 1ULL << 8
const RegVal	STATUS_MPIE_MASK = 1ULL << 7
const RegVal	STATUS_UBE_MASK = 1ULL << 6
const RegVal	STATUS_SPIE_MASK = 1ULL << 5
const RegVal	STATUS_MIE_MASK = 1ULL << 3
const RegVal	STATUS_SIE_MASK = 1ULL << 1
const RegVal	HSTATUS_VSXL_MASK = 3ULL << VSXL_OFFSET
const RegVal	HSTATUS_VTSR_MASK = 1ULL << 22
const RegVal	HSTATUS_VTW_MASK = 1ULL << 21
const RegVal	HSTATUS_VTVM_MASK = 1ULL << 20
const RegVal	HSTATUS_VGEIN_MASK = 63ULL << 12
const RegVal	HSTATUS_HU_MASK = 1ULL << 9
const RegVal	HSTATUS_SPVP_MASK = 1ULL << 8
const RegVal	HSTATUS_SPV_MASK = 1ULL << 7
const RegVal	HSTATUS_GVA_MASK = 1LL << 6
const RegVal	HSTATUS_VSBE_MASK = 1ULL << 5
const RegVal	MSTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const RegVal	MSTATUSH_MASKS [enums::Num_PrivilegeModeSet]
const RegVal	HSTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const RegVal	SSTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const RegVal	LOCAL_MASK = mask(63,16)
const RegVal	SGEI_MASK = 1ULL << 12
const RegVal	MEI_MASK = 1ULL << 11
const RegVal	VSEI_MASK = 1ULL << 10
const RegVal	SEI_MASK = 1ULL << 9
const RegVal	MTI_MASK = 1ULL << 7
const RegVal	VSTI_MASK = 1ULL << 6
const RegVal	STI_MASK = 1ULL << 5
const RegVal	MSI_MASK = 1ULL << 3
const RegVal	VSSI_MASK = 1ULL << 2
const RegVal	SSI_MASK = 1ULL << 1
const RegVal	MI_MASK [enums::Num_PrivilegeModeSet]
const RegVal	SI_MASK [enums::Num_PrivilegeModeSet]
const RegVal	MIDELEG_MASK [enums::Num_PrivilegeModeSet]
const RegVal	VSI_MASK [enums::Num_PrivilegeModeSet]
const RegVal	FFLAGS_MASK = (1 << FRM_OFFSET) - 1
const RegVal	FRM_MASK = 0x7
const RegVal	CAUSE_INTERRUPT_MASKS [enums::Num_RiscvType]
const RegVal	DELEGABLE_INTS_MASK
const RegVal	HS_INTERRUPTS = SGEI_MASK | VSSI_MASK | VSTI_MASK | VSEI_MASK
const std::unordered_map< int, RegVal >	CSRMasks [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const std::unordered_map< int, RegVal >	CSRWriteMasks [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const int	NumVecStandardRegs = 32
const int	NumVecInternalRegs = 8
const int	NumVecRegs = NumVecStandardRegs + NumVecInternalRegs
const std::vector< std::string >	VecRegNames
const int	VecMemInternalReg0 = NumVecStandardRegs
static TypedRegClassOps< RiscvISA::VecRegContainer >	vecRegClassOps
constexpr RegClass	vecRegClass
Bitfield< 7, 0 >	vtype8
Bitfield< 7 >	vma
Bitfield< 6 >	vta
Bitfield< 5, 3 >	vsew
Bitfield< 2, 0 >	vlmul
const uint8_t	_rvk_emu_aes_fwd_sbox [256]
	Ref: https://github.com/rvkrypto/rvkrypto-fips.
const uint8_t	_rvk_emu_aes_inv_sbox [256]
const uint8_t	_rvk_emu_sm4_sbox [256]
	rv_type
Bitfield< 61 >	compressed
Bitfield< 60 >	enable_zcd
Bitfield< 57, 41 >	vl
Bitfield< 40 >	vill
Bitfield< 1, 0 >	quadRant
Bitfield< 6, 2 >	opcode5
Bitfield< 6, 0 >	opcode
Bitfield< 31, 0 >	all
Bitfield< 11, 7 >	rd
Bitfield< 14, 12 >	funct3
Bitfield< 19, 15 >	rs1
Bitfield< 24, 20 >	rs2
Bitfield< 31, 25 >	funct7
Bitfield< 30 >	srType
Bitfield< 24, 20 >	shamt5
Bitfield< 25, 20 >	shamt6
Bitfield< 31, 20 >	imm12
Bitfield< 23, 20 >	succ
Bitfield< 27, 24 >	pred
Bitfield< 11, 7 >	imm5
Bitfield< 31, 25 >	imm7
Bitfield< 31, 12 >	imm20
Bitfield< 7 >	bimm12bit11
Bitfield< 11, 8 >	bimm12bits4to1
Bitfield< 30, 25 >	bimm12bits10to5
Bitfield< 31 >	immsign
Bitfield< 30, 21 >	ujimmbits10to1
Bitfield< 20 >	ujimmbit11
Bitfield< 19, 12 >	ujimmbits19to12
Bitfield< 31, 20 >	funct12
Bitfield< 19, 15 >	csrimm
Bitfield< 11, 7 >	fd
Bitfield< 19, 15 >	fs1
Bitfield< 24, 20 >	fs2
Bitfield< 31, 27 >	fs3
Bitfield< 14, 12 >	round_mode
Bitfield< 24, 20 >	conv_sgn
Bitfield< 26, 25 >	funct2
Bitfield< 31, 27 >	amofunct
Bitfield< 26 >	aq
Bitfield< 25 >	rl
Bitfield< 15, 13 >	copcode
Bitfield< 12 >	cfunct1
Bitfield< 11, 10 >	cfunct2high
Bitfield< 6, 5 >	cfunct2low
Bitfield< 11, 7 >	rc1
Bitfield< 6, 2 >	rc2
Bitfield< 9, 7 >	rp1
Bitfield< 4, 2 >	rp2
Bitfield< 9, 7 >	r1s
Bitfield< 4, 2 >	r2s
Bitfield< 11, 7 >	fc1
Bitfield< 6, 2 >	fc2
Bitfield< 4, 2 >	fp2
Bitfield< 12, 2 >	cjumpimm
Bitfield< 5, 3 >	cjumpimm3to1
Bitfield< 11, 11 >	cjumpimm4to4
Bitfield< 2, 2 >	cjumpimm5to5
Bitfield< 7, 7 >	cjumpimm6to6
Bitfield< 6, 6 >	cjumpimm7to7
Bitfield< 10, 9 >	cjumpimm9to8
Bitfield< 8, 8 >	cjumpimm10to10
Bitfield< 12 >	cjumpimmsign
Bitfield< 12, 5 >	cimm8
Bitfield< 12, 7 >	cimm6
Bitfield< 6, 2 >	cimm5
Bitfield< 12, 10 >	cimm3
Bitfield< 6, 5 >	cimm2
Bitfield< 12 >	cimm1
Bitfield< 7, 4 >	rlist
Bitfield< 3, 2 >	spimm
Bitfield< 9, 2 >	jt_index
Bitfield< 31, 25 >	m5func
Bitfield< 31, 26 >	vfunct6
Bitfield< 31, 27 >	vfunct5
Bitfield< 27, 25 >	vfunct3
Bitfield< 26, 25 >	vfunct2
Bitfield< 31, 29 >	nf
Bitfield< 28 >	mew
Bitfield< 27, 26 >	mop
Bitfield< 25 >	vm
Bitfield< 24, 20 >	lumop
Bitfield< 24, 20 >	sumop
Bitfield< 14, 12 >	width
Bitfield< 24, 20 >	vs2
Bitfield< 19, 15 >	vs1
Bitfield< 11, 7 >	vd
Bitfield< 11, 7 >	vs3
Bitfield< 19, 15 >	vecimm
Bitfield< 17, 15 >	simm3
Bitfield< 31 >	bit31
Bitfield< 30 >	bit30
Bitfield< 30, 20 >	zimm_vsetvli
Bitfield< 31, 30 >	bit31_30
Bitfield< 29, 20 >	zimm_vsetivli
Bitfield< 19, 15 >	uimm_vsetivli
Bitfield< 31, 25 >	bit31_25
constexpr unsigned	MaxVecLenInBytes = MaxVecLenInBits >> 3

Typedef Documentation

freg_t

using gem5::RiscvISA::freg_t = float64_t

Definition at line 69 of file float.hh.

MachInst

typedef uint32_t gem5::RiscvISA::MachInst

Definition at line 53 of file types.hh.

PrivilegeModeSet

using gem5::RiscvISA::PrivilegeModeSet = enums::PrivilegeModeSet

Definition at line 59 of file pcstate.hh.

RiscvType

using gem5::RiscvISA::RiscvType = enums::RiscvType

Definition at line 55 of file pcstate.hh.

TlbEntryTrie

typedef Trie<Addr, TlbEntry> gem5::RiscvISA::TlbEntryTrie

Definition at line 92 of file pagetable.hh.

VecRegContainer

using gem5::RiscvISA::VecRegContainer = gem5::VecRegContainer<MaxVecLenInBytes>

Definition at line 50 of file vector.hh.

VPUStatus

using gem5::RiscvISA::VPUStatus = FPUStatus

Definition at line 74 of file isa.hh.

vreg_t

using gem5::RiscvISA::vreg_t = VecRegContainer

Definition at line 51 of file vector.hh.

Enumeration Type Documentation

CSRIndex

enum gem5::RiscvISA::CSRIndex

Enumerator
CSR_FFLAGS
CSR_FRM
CSR_FCSR
CSR_CYCLE
CSR_TIME
CSR_INSTRET
CSR_HPMCOUNTER03
CSR_HPMCOUNTER04
CSR_HPMCOUNTER05
CSR_HPMCOUNTER06
CSR_HPMCOUNTER07
CSR_HPMCOUNTER08
CSR_HPMCOUNTER09
CSR_HPMCOUNTER10
CSR_HPMCOUNTER11
CSR_HPMCOUNTER12
CSR_HPMCOUNTER13
CSR_HPMCOUNTER14
CSR_HPMCOUNTER15
CSR_HPMCOUNTER16
CSR_HPMCOUNTER17
CSR_HPMCOUNTER18
CSR_HPMCOUNTER19
CSR_HPMCOUNTER20
CSR_HPMCOUNTER21
CSR_HPMCOUNTER22
CSR_HPMCOUNTER23
CSR_HPMCOUNTER24
CSR_HPMCOUNTER25
CSR_HPMCOUNTER26
CSR_HPMCOUNTER27
CSR_HPMCOUNTER28
CSR_HPMCOUNTER29
CSR_HPMCOUNTER30
CSR_HPMCOUNTER31
CSR_CYCLEH
CSR_TIMEH
CSR_INSTRETH
CSR_HPMCOUNTER03H
CSR_HPMCOUNTER04H
CSR_HPMCOUNTER05H
CSR_HPMCOUNTER06H
CSR_HPMCOUNTER07H
CSR_HPMCOUNTER08H
CSR_HPMCOUNTER09H
CSR_HPMCOUNTER10H
CSR_HPMCOUNTER11H
CSR_HPMCOUNTER12H
CSR_HPMCOUNTER13H
CSR_HPMCOUNTER14H
CSR_HPMCOUNTER15H
CSR_HPMCOUNTER16H
CSR_HPMCOUNTER17H
CSR_HPMCOUNTER18H
CSR_HPMCOUNTER19H
CSR_HPMCOUNTER20H
CSR_HPMCOUNTER21H
CSR_HPMCOUNTER22H
CSR_HPMCOUNTER23H
CSR_HPMCOUNTER24H
CSR_HPMCOUNTER25H
CSR_HPMCOUNTER26H
CSR_HPMCOUNTER27H
CSR_HPMCOUNTER28H
CSR_HPMCOUNTER29H
CSR_HPMCOUNTER30H
CSR_HPMCOUNTER31H
CSR_SSTATUS
CSR_SIE
CSR_STVEC
CSR_SCOUNTEREN
CSR_SSCRATCH
CSR_SEPC
CSR_SCAUSE
CSR_STVAL
CSR_SIP
CSR_SATP
CSR_SENVCFG
CSR_MVENDORID
CSR_MARCHID
CSR_MIMPID
CSR_MHARTID
CSR_MSTATUS
CSR_MISA
CSR_MEDELEG
CSR_MIDELEG
CSR_MIE
CSR_MTVEC
CSR_MCOUNTEREN
CSR_MSTATUSH
CSR_MSCRATCH
CSR_MEPC
CSR_MCAUSE
CSR_MTVAL
CSR_MIP
CSR_PMPCFG0
CSR_PMPCFG1
CSR_PMPCFG2
CSR_PMPCFG3
CSR_PMPADDR00
CSR_PMPADDR01
CSR_PMPADDR02
CSR_PMPADDR03
CSR_PMPADDR04
CSR_PMPADDR05
CSR_PMPADDR06
CSR_PMPADDR07
CSR_PMPADDR08
CSR_PMPADDR09
CSR_PMPADDR10
CSR_PMPADDR11
CSR_PMPADDR12
CSR_PMPADDR13
CSR_PMPADDR14
CSR_PMPADDR15
CSR_MCYCLE
CSR_MINSTRET
CSR_MHPMCOUNTER03
CSR_MHPMCOUNTER04
CSR_MHPMCOUNTER05
CSR_MHPMCOUNTER06
CSR_MHPMCOUNTER07
CSR_MHPMCOUNTER08
CSR_MHPMCOUNTER09
CSR_MHPMCOUNTER10
CSR_MHPMCOUNTER11
CSR_MHPMCOUNTER12
CSR_MHPMCOUNTER13
CSR_MHPMCOUNTER14
CSR_MHPMCOUNTER15
CSR_MHPMCOUNTER16
CSR_MHPMCOUNTER17
CSR_MHPMCOUNTER18
CSR_MHPMCOUNTER19
CSR_MHPMCOUNTER20
CSR_MHPMCOUNTER21
CSR_MHPMCOUNTER22
CSR_MHPMCOUNTER23
CSR_MHPMCOUNTER24
CSR_MHPMCOUNTER25
CSR_MHPMCOUNTER26
CSR_MHPMCOUNTER27
CSR_MHPMCOUNTER28
CSR_MHPMCOUNTER29
CSR_MHPMCOUNTER30
CSR_MHPMCOUNTER31
CSR_MCYCLEH
CSR_MINSTRETH
CSR_MHPMCOUNTER03H
CSR_MHPMCOUNTER04H
CSR_MHPMCOUNTER05H
CSR_MHPMCOUNTER06H
CSR_MHPMCOUNTER07H
CSR_MHPMCOUNTER08H
CSR_MHPMCOUNTER09H
CSR_MHPMCOUNTER10H
CSR_MHPMCOUNTER11H
CSR_MHPMCOUNTER12H
CSR_MHPMCOUNTER13H
CSR_MHPMCOUNTER14H
CSR_MHPMCOUNTER15H
CSR_MHPMCOUNTER16H
CSR_MHPMCOUNTER17H
CSR_MHPMCOUNTER18H
CSR_MHPMCOUNTER19H
CSR_MHPMCOUNTER20H
CSR_MHPMCOUNTER21H
CSR_MHPMCOUNTER22H
CSR_MHPMCOUNTER23H
CSR_MHPMCOUNTER24H
CSR_MHPMCOUNTER25H
CSR_MHPMCOUNTER26H
CSR_MHPMCOUNTER27H
CSR_MHPMCOUNTER28H
CSR_MHPMCOUNTER29H
CSR_MHPMCOUNTER30H
CSR_MHPMCOUNTER31H
CSR_MHPMEVENT03
CSR_MHPMEVENT04
CSR_MHPMEVENT05
CSR_MHPMEVENT06
CSR_MHPMEVENT07
CSR_MHPMEVENT08
CSR_MHPMEVENT09
CSR_MHPMEVENT10
CSR_MHPMEVENT11
CSR_MHPMEVENT12
CSR_MHPMEVENT13
CSR_MHPMEVENT14
CSR_MHPMEVENT15
CSR_MHPMEVENT16
CSR_MHPMEVENT17
CSR_MHPMEVENT18
CSR_MHPMEVENT19
CSR_MHPMEVENT20
CSR_MHPMEVENT21
CSR_MHPMEVENT22
CSR_MHPMEVENT23
CSR_MHPMEVENT24
CSR_MHPMEVENT25
CSR_MHPMEVENT26
CSR_MHPMEVENT27
CSR_MHPMEVENT28
CSR_MHPMEVENT29
CSR_MHPMEVENT30
CSR_MHPMEVENT31
CSR_TSELECT
CSR_TDATA1
CSR_TDATA2
CSR_TDATA3
CSR_DCSR
CSR_DPC
CSR_DSCRATCH
CSR_VSTART
CSR_VXSAT
CSR_VXRM
CSR_VCSR
CSR_VL
CSR_VTYPE
CSR_VLENB
CSR_MNSCRATCH
CSR_MNEPC
CSR_MNCAUSE
CSR_MNSTATUS
CSR_JVT
CSR_MTINST
CSR_MTVAL2
CSR_HSTATUS
CSR_HEDELEG
CSR_HIDELEG
CSR_HIE
CSR_HTIMEDELTA
CSR_HCOUNTEREN
CSR_HGEIE
CSR_HTVAL
CSR_HIP
CSR_HVIP
CSR_HTINST
CSR_HGEIP
CSR_HENVCFG
CSR_HGATP
CSR_HCONTEXT
CSR_VSSTATUS
CSR_VSIE
CSR_VSTVEC
CSR_VSSCRATCH
CSR_VSEPC
CSR_VSCAUSE
CSR_VSTVAL
CSR_VSIP
CSR_VSATP

Definition at line 304 of file misc.hh.

ExceptionCode

enum gem5::RiscvISA::ExceptionCode : uint64_t

Enumerator
INST_ADDR_MISALIGNED
INST_ACCESS
INST_ILLEGAL
BREAKPOINT
LOAD_ADDR_MISALIGNED
LOAD_ACCESS
STORE_ADDR_MISALIGNED
AMO_ADDR_MISALIGNED
STORE_ACCESS
AMO_ACCESS
ECALL_USER
ECALL_SUPER
ECALL_VIRTUAL_SUPER
ECALL_MACHINE
INST_PAGE
LOAD_PAGE
STORE_PAGE
AMO_PAGE
INST_GUEST_PAGE
LOAD_GUEST_PAGE
VIRTUAL_INST
STORE_GUEST_PAGE
AMO_GUEST_PAGE
INT_SOFTWARE_SUPER
INT_SOFTWARE_VIRTUAL_SUPER
INT_SOFTWARE_MACHINE
INT_TIMER_SUPER
INT_TIMER_VIRTUAL_SUPER
INT_TIMER_MACHINE
INT_EXT_SUPER
INT_EXT_VIRTUAL_SUPER
INT_EXT_MACHINE
INT_EXT_SUPER_GUEST
INT_LOCAL_0
INT_LOCAL_1
INT_LOCAL_2
INT_LOCAL_3
INT_LOCAL_4
INT_LOCAL_5
INT_LOCAL_6
INT_LOCAL_7
INT_LOCAL_8
INT_LOCAL_9
INT_LOCAL_10
INT_LOCAL_11
INT_LOCAL_12
INT_LOCAL_13
INT_LOCAL_14
INT_LOCAL_15
INT_LOCAL_16
INT_LOCAL_17
INT_LOCAL_18
INT_LOCAL_19
INT_LOCAL_20
INT_LOCAL_21
INT_LOCAL_22
INT_LOCAL_23
INT_LOCAL_24
INT_LOCAL_25
INT_LOCAL_26
INT_LOCAL_27
INT_LOCAL_28
INT_LOCAL_29
INT_LOCAL_30
INT_LOCAL_31
INT_LOCAL_32
INT_LOCAL_33
INT_LOCAL_34
INT_LOCAL_35
INT_LOCAL_36
INT_LOCAL_37
INT_LOCAL_38
INT_LOCAL_39
INT_LOCAL_40
INT_LOCAL_41
INT_LOCAL_42
INT_LOCAL_43
INT_LOCAL_44
INT_LOCAL_45
INT_LOCAL_46
INT_LOCAL_47
NumInterruptTypes
INT_NMI

Definition at line 60 of file fault_codes.hh.

FaultType

enum class gem5::RiscvISA::FaultType

strong

Enumerator
INTERRUPT
NON_MASKABLE_INTERRUPT
OTHERS

Definition at line 51 of file faults.hh.

FloatException

enum gem5::RiscvISA::FloatException : uint64_t

Enumerator
FloatInexact
FloatUnderflow
FloatOverflow
FloatDivZero
FloatInvalid

Definition at line 42 of file fault_codes.hh.

FPUStatus

enum gem5::RiscvISA::FPUStatus

Enumerator
OFF
INITIAL
CLEAN
DIRTY

Definition at line 66 of file isa.hh.

MiscRegIndex

enum gem5::RiscvISA::MiscRegIndex

Enumerator
MISCREG_PRV
MISCREG_ISA
MISCREG_VENDORID
MISCREG_ARCHID
MISCREG_IMPID
MISCREG_HARTID
MISCREG_STATUS
MISCREG_IP
MISCREG_IE
MISCREG_CYCLE
MISCREG_TIME
MISCREG_INSTRET
MISCREG_HPMCOUNTER03
MISCREG_HPMCOUNTER04
MISCREG_HPMCOUNTER05
MISCREG_HPMCOUNTER06
MISCREG_HPMCOUNTER07
MISCREG_HPMCOUNTER08
MISCREG_HPMCOUNTER09
MISCREG_HPMCOUNTER10
MISCREG_HPMCOUNTER11
MISCREG_HPMCOUNTER12
MISCREG_HPMCOUNTER13
MISCREG_HPMCOUNTER14
MISCREG_HPMCOUNTER15
MISCREG_HPMCOUNTER16
MISCREG_HPMCOUNTER17
MISCREG_HPMCOUNTER18
MISCREG_HPMCOUNTER19
MISCREG_HPMCOUNTER20
MISCREG_HPMCOUNTER21
MISCREG_HPMCOUNTER22
MISCREG_HPMCOUNTER23
MISCREG_HPMCOUNTER24
MISCREG_HPMCOUNTER25
MISCREG_HPMCOUNTER26
MISCREG_HPMCOUNTER27
MISCREG_HPMCOUNTER28
MISCREG_HPMCOUNTER29
MISCREG_HPMCOUNTER30
MISCREG_HPMCOUNTER31
MISCREG_HPMEVENT03
MISCREG_HPMEVENT04
MISCREG_HPMEVENT05
MISCREG_HPMEVENT06
MISCREG_HPMEVENT07
MISCREG_HPMEVENT08
MISCREG_HPMEVENT09
MISCREG_HPMEVENT10
MISCREG_HPMEVENT11
MISCREG_HPMEVENT12
MISCREG_HPMEVENT13
MISCREG_HPMEVENT14
MISCREG_HPMEVENT15
MISCREG_HPMEVENT16
MISCREG_HPMEVENT17
MISCREG_HPMEVENT18
MISCREG_HPMEVENT19
MISCREG_HPMEVENT20
MISCREG_HPMEVENT21
MISCREG_HPMEVENT22
MISCREG_HPMEVENT23
MISCREG_HPMEVENT24
MISCREG_HPMEVENT25
MISCREG_HPMEVENT26
MISCREG_HPMEVENT27
MISCREG_HPMEVENT28
MISCREG_HPMEVENT29
MISCREG_HPMEVENT30
MISCREG_HPMEVENT31
MISCREG_TSELECT
MISCREG_TDATA1
MISCREG_TDATA2
MISCREG_TDATA3
MISCREG_DCSR
MISCREG_DPC
MISCREG_DSCRATCH
MISCREG_MEDELEG
MISCREG_MIDELEG
MISCREG_MTVEC
MISCREG_MCOUNTEREN
MISCREG_MSCRATCH
MISCREG_MEPC
MISCREG_MCAUSE
MISCREG_MTVAL
MISCREG_PMPCFG0
MISCREG_PMPCFG1
MISCREG_PMPCFG2
MISCREG_PMPCFG3
MISCREG_PMPADDR00
MISCREG_PMPADDR01
MISCREG_PMPADDR02
MISCREG_PMPADDR03
MISCREG_PMPADDR04
MISCREG_PMPADDR05
MISCREG_PMPADDR06
MISCREG_PMPADDR07
MISCREG_PMPADDR08
MISCREG_PMPADDR09
MISCREG_PMPADDR10
MISCREG_PMPADDR11
MISCREG_PMPADDR12
MISCREG_PMPADDR13
MISCREG_PMPADDR14
MISCREG_PMPADDR15
MISCREG_RESERVED01
MISCREG_RESERVED02
MISCREG_STVEC
MISCREG_SCOUNTEREN
MISCREG_SSCRATCH
MISCREG_SEPC
MISCREG_SCAUSE
MISCREG_STVAL
MISCREG_SATP
MISCREG_SENVCFG
MISCREG_RESERVED03
MISCREG_RESERVED04
MISCREG_RESERVED05
MISCREG_RESERVED06
MISCREG_RESERVED07
MISCREG_FFLAGS
MISCREG_FRM
MISCREG_VSTART
MISCREG_VXSAT
MISCREG_VXRM
MISCREG_VCSR
MISCREG_VL
MISCREG_VTYPE
MISCREG_VLENB
MISCREG_HVIP
MISCREG_MTINST
MISCREG_MTVAL2
MISCREG_HSTATUS
MISCREG_HEDELEG
MISCREG_HIDELEG
MISCREG_HCOUNTEREN
MISCREG_HGEIE
MISCREG_HTVAL
MISCREG_HTINST
MISCREG_HGEIP
MISCREG_HENVCFG
MISCREG_HGATP
MISCREG_HCONTEXT
MISCREG_HTIMEDELTA
MISCREG_VSSTATUS
MISCREG_VSTVEC
MISCREG_VSSCRATCH
MISCREG_VSEPC
MISCREG_VSCAUSE
MISCREG_VSTVAL
MISCREG_VSATP
MISCREG_VIRT
MISCREG_NMIVEC
MISCREG_NMIE
MISCREG_NMIP
MISCREG_MNSCRATCH
MISCREG_MNEPC
MISCREG_MNCAUSE
MISCREG_MNSTATUS
MISCREG_MSTATUSH
MISCREG_CYCLEH
MISCREG_TIMEH
MISCREG_INSTRETH
MISCREG_HPMCOUNTER03H
MISCREG_HPMCOUNTER04H
MISCREG_HPMCOUNTER05H
MISCREG_HPMCOUNTER06H
MISCREG_HPMCOUNTER07H
MISCREG_HPMCOUNTER08H
MISCREG_HPMCOUNTER09H
MISCREG_HPMCOUNTER10H
MISCREG_HPMCOUNTER11H
MISCREG_HPMCOUNTER12H
MISCREG_HPMCOUNTER13H
MISCREG_HPMCOUNTER14H
MISCREG_HPMCOUNTER15H
MISCREG_HPMCOUNTER16H
MISCREG_HPMCOUNTER17H
MISCREG_HPMCOUNTER18H
MISCREG_HPMCOUNTER19H
MISCREG_HPMCOUNTER20H
MISCREG_HPMCOUNTER21H
MISCREG_HPMCOUNTER22H
MISCREG_HPMCOUNTER23H
MISCREG_HPMCOUNTER24H
MISCREG_HPMCOUNTER25H
MISCREG_HPMCOUNTER26H
MISCREG_HPMCOUNTER27H
MISCREG_HPMCOUNTER28H
MISCREG_HPMCOUNTER29H
MISCREG_HPMCOUNTER30H
MISCREG_HPMCOUNTER31H
MISCREG_JVT
NUM_PHYS_MISCREGS
MISCREG_FFLAGS_EXE
NUM_MISCREGS

Definition at line 70 of file misc.hh.

PrivilegeMode

enum gem5::RiscvISA::PrivilegeMode

Enumerator
PRV_U
PRV_S
PRV_HS
PRV_M

Definition at line 57 of file isa.hh.

XlateFlags

enum gem5::RiscvISA::XlateFlags

Enumerator
HLVX
FORCE_VIRT
LR

Definition at line 44 of file memflags.hh.

XlateStage

enum gem5::RiscvISA::XlateStage

Enumerator
FIRST_STAGE
GSTAGE

Definition at line 78 of file tlb.hh.

Function Documentation

_rvk_emu_aes32dsi()

int32_t gem5::RiscvISA::_rvk_emu_aes32dsi ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 361 of file rvk.hh.

References _rvk_emu_aes_inv_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32dsmi()

int32_t gem5::RiscvISA::_rvk_emu_aes32dsmi ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 372 of file rvk.hh.

References _rvk_emu_aes_inv_mc_8(), _rvk_emu_aes_inv_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32esi()

int32_t gem5::RiscvISA::_rvk_emu_aes32esi ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 447 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32esmi()

int32_t gem5::RiscvISA::_rvk_emu_aes32esmi ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 458 of file rvk.hh.

References _rvk_emu_aes_fwd_mc_8(), _rvk_emu_aes_fwd_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes64ds()

int64_t gem5::RiscvISA::_rvk_emu_aes64ds ( int64_t rs1, int64_t rs2 )

inline

Definition at line 384 of file rvk.hh.

References _rvk_emu_aes_inv_sbox, rs1, and rs2.

Referenced by _rvk_emu_aes64dsm().

_rvk_emu_aes64dsm()

int64_t gem5::RiscvISA::_rvk_emu_aes64dsm ( int64_t rs1, int64_t rs2 )

inline

Definition at line 402 of file rvk.hh.

References _rvk_emu_aes64ds(), _rvk_emu_aes64im(), rs1, rs2, and x.

_rvk_emu_aes64es()

int64_t gem5::RiscvISA::_rvk_emu_aes64es ( int64_t rs1, int64_t rs2 )

inline

Definition at line 470 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, rs1, and rs2.

Referenced by _rvk_emu_aes64esm().

_rvk_emu_aes64esm()

int64_t gem5::RiscvISA::_rvk_emu_aes64esm ( int64_t rs1, int64_t rs2 )

inline

Definition at line 482 of file rvk.hh.

References _rvk_emu_aes64es(), _rvk_emu_aes_fwd_mc_32(), rs1, rs2, and x.

_rvk_emu_aes64im()

int64_t gem5::RiscvISA::_rvk_emu_aes64im ( int64_t rs1 )

inline

Definition at line 396 of file rvk.hh.

References _rvk_emu_aes_inv_mc_32(), and rs1.

Referenced by _rvk_emu_aes64dsm().

_rvk_emu_aes64ks1i()

int64_t gem5::RiscvISA::_rvk_emu_aes64ks1i ( int64_t rs1, int rnum )

inline

Definition at line 411 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, _rvk_emu_ror_32(), gem5::PowerISA::rc, rs1, and gem5::ArmISA::t.

_rvk_emu_aes64ks2()

int64_t gem5::RiscvISA::_rvk_emu_aes64ks2 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 437 of file rvk.hh.

References rs1, rs2, and gem5::ArmISA::t.

_rvk_emu_aes_fwd_mc_32()

uint32_t gem5::RiscvISA::_rvk_emu_aes_fwd_mc_32 ( uint32_t x )

inline

Definition at line 326 of file rvk.hh.

References _rvk_emu_aes_fwd_mc_8(), _rvk_emu_rol_32(), and x.

Referenced by _rvk_emu_aes64esm().

_rvk_emu_aes_fwd_mc_8()

uint32_t gem5::RiscvISA::_rvk_emu_aes_fwd_mc_8 ( uint32_t x )

inline

Definition at line 317 of file rvk.hh.

References _rvk_emu_aes_xtime(), and x.

Referenced by _rvk_emu_aes32esmi(), and _rvk_emu_aes_fwd_mc_32().

_rvk_emu_aes_inv_mc_32()

uint32_t gem5::RiscvISA::_rvk_emu_aes_inv_mc_32 ( uint32_t x )

inline

Definition at line 352 of file rvk.hh.

References _rvk_emu_aes_inv_mc_8(), _rvk_emu_rol_32(), and x.

Referenced by _rvk_emu_aes64im().

_rvk_emu_aes_inv_mc_8()

uint32_t gem5::RiscvISA::_rvk_emu_aes_inv_mc_8 ( uint32_t x )

inline

Definition at line 335 of file rvk.hh.

References _rvk_emu_aes_xtime(), and x.

Referenced by _rvk_emu_aes32dsmi(), and _rvk_emu_aes_inv_mc_32().

_rvk_emu_aes_xtime()

uint8_t gem5::RiscvISA::_rvk_emu_aes_xtime ( uint8_t x )

inline

Definition at line 311 of file rvk.hh.

References x.

Referenced by _rvk_emu_aes_fwd_mc_8(), and _rvk_emu_aes_inv_mc_8().

_rvk_emu_brev8_32()

int32_t gem5::RiscvISA::_rvk_emu_brev8_32 ( int32_t rs1 )

inline

Definition at line 182 of file rvk.hh.

References _rvk_emu_grev_32(), and rs1.

_rvk_emu_brev8_64()

int64_t gem5::RiscvISA::_rvk_emu_brev8_64 ( int64_t rs1 )

inline

Definition at line 185 of file rvk.hh.

References _rvk_emu_grev_64(), and rs1.

_rvk_emu_clmul_32()

int32_t gem5::RiscvISA::_rvk_emu_clmul_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 229 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmul_64()

int64_t gem5::RiscvISA::_rvk_emu_clmul_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 249 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmulh_32()

int32_t gem5::RiscvISA::_rvk_emu_clmulh_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 239 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmulh_64()

int64_t gem5::RiscvISA::_rvk_emu_clmulh_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 260 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_grev_32()

int32_t gem5::RiscvISA::_rvk_emu_grev_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 145 of file rvk.hh.

References rs1, rs2, and x.

Referenced by _rvk_emu_brev8_32().

_rvk_emu_grev_64()

int64_t gem5::RiscvISA::_rvk_emu_grev_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 157 of file rvk.hh.

References rs1, rs2, and x.

Referenced by _rvk_emu_brev8_64().

_rvk_emu_rol_32()

int32_t gem5::RiscvISA::_rvk_emu_rol_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 134 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes_fwd_mc_32(), _rvk_emu_aes_inv_mc_32(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), and _rvk_emu_sm4ks().

_rvk_emu_rol_64()

int64_t gem5::RiscvISA::_rvk_emu_rol_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 139 of file rvk.hh.

References _rvk_emu_sll_64(), _rvk_emu_srl_64(), rs1, and rs2.

_rvk_emu_ror_32()

int32_t gem5::RiscvISA::_rvk_emu_ror_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 136 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

Referenced by _rvk_emu_aes64ks1i(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), and _rvk_emu_sha256sum1().

_rvk_emu_ror_64()

int64_t gem5::RiscvISA::_rvk_emu_ror_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 141 of file rvk.hh.

References _rvk_emu_sll_64(), _rvk_emu_srl_64(), rs1, and rs2.

Referenced by _rvk_emu_sha512sig0(), _rvk_emu_sha512sig1(), _rvk_emu_sha512sum0(), and _rvk_emu_sha512sum1().

_rvk_emu_sha256sig0()

int32_t gem5::RiscvISA::_rvk_emu_sha256sig0 ( int32_t rs1 )

inline

Definition at line 492 of file rvk.hh.

References _rvk_emu_ror_32(), _rvk_emu_srl_32(), rs1, and x.

_rvk_emu_sha256sig1()

int32_t gem5::RiscvISA::_rvk_emu_sha256sig1 ( int32_t rs1 )

inline

Definition at line 501 of file rvk.hh.

References _rvk_emu_ror_32(), _rvk_emu_srl_32(), rs1, and x.

_rvk_emu_sha256sum0()

int32_t gem5::RiscvISA::_rvk_emu_sha256sum0 ( int32_t rs1 )

inline

Definition at line 510 of file rvk.hh.

References _rvk_emu_ror_32(), rs1, and x.

_rvk_emu_sha256sum1()

int32_t gem5::RiscvISA::_rvk_emu_sha256sum1 ( int32_t rs1 )

inline

Definition at line 519 of file rvk.hh.

References _rvk_emu_ror_32(), rs1, and x.

_rvk_emu_sha512sig0()

int64_t gem5::RiscvISA::_rvk_emu_sha512sig0 ( int64_t rs1 )

inline

Definition at line 570 of file rvk.hh.

References _rvk_emu_ror_64(), _rvk_emu_srl_64(), and rs1.

_rvk_emu_sha512sig0h()

int32_t gem5::RiscvISA::_rvk_emu_sha512sig0h ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 528 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig0l()

int32_t gem5::RiscvISA::_rvk_emu_sha512sig0l ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 535 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig1()

int64_t gem5::RiscvISA::_rvk_emu_sha512sig1 ( int64_t rs1 )

inline

Definition at line 576 of file rvk.hh.

References _rvk_emu_ror_64(), _rvk_emu_srl_64(), and rs1.

_rvk_emu_sha512sig1h()

int32_t gem5::RiscvISA::_rvk_emu_sha512sig1h ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 542 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig1l()

int32_t gem5::RiscvISA::_rvk_emu_sha512sig1l ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 549 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sum0()

int64_t gem5::RiscvISA::_rvk_emu_sha512sum0 ( int64_t rs1 )

inline

Definition at line 582 of file rvk.hh.

References _rvk_emu_ror_64(), and rs1.

_rvk_emu_sha512sum0r()

int32_t gem5::RiscvISA::_rvk_emu_sha512sum0r ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 556 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sum1()

int64_t gem5::RiscvISA::_rvk_emu_sha512sum1 ( int64_t rs1 )

inline

Definition at line 588 of file rvk.hh.

References _rvk_emu_ror_64(), and rs1.

_rvk_emu_sha512sum1r()

int32_t gem5::RiscvISA::_rvk_emu_sha512sum1r ( int32_t rs1, int32_t rs2 )

inlinestatic

Definition at line 563 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_shfl_32()

int32_t gem5::RiscvISA::_rvk_emu_shfl_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 196 of file rvk.hh.

References _rvk_emu_shuffle32_stage(), rs1, rs2, and x.

Referenced by _rvk_emu_zip_32().

_rvk_emu_shuffle32_stage()

uint32_t gem5::RiscvISA::_rvk_emu_shuffle32_stage ( uint32_t src, uint32_t maskL, uint32_t maskR, int N )

inline

Definition at line 188 of file rvk.hh.

References x.

Referenced by _rvk_emu_shfl_32(), and _rvk_emu_unshfl_32().

_rvk_emu_sll_32()

int32_t gem5::RiscvISA::_rvk_emu_sll_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 124 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_32(), _rvk_emu_ror_32(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), and _rvk_emu_sha512sum1r().

_rvk_emu_sll_64()

int64_t gem5::RiscvISA::_rvk_emu_sll_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 128 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_64(), and _rvk_emu_ror_64().

_rvk_emu_sm3p0()

int32_t gem5::RiscvISA::_rvk_emu_sm3p0 ( int32_t rs1 )

inline

Definition at line 624 of file rvk.hh.

References _rvk_emu_rol_32(), rs1, and x.

_rvk_emu_sm3p1()

int32_t gem5::RiscvISA::_rvk_emu_sm3p1 ( int32_t rs1 )

inline

Definition at line 632 of file rvk.hh.

References _rvk_emu_rol_32(), rs1, and x.

_rvk_emu_sm4ed()

int32_t gem5::RiscvISA::_rvk_emu_sm4ed ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 595 of file rvk.hh.

References _rvk_emu_rol_32(), _rvk_emu_sm4_sbox, gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_sm4ks()

int32_t gem5::RiscvISA::_rvk_emu_sm4ks ( int32_t rs1, int32_t rs2, uint8_t bs )

inline

Definition at line 609 of file rvk.hh.

References _rvk_emu_rol_32(), _rvk_emu_sm4_sbox, gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_srl_32()

int32_t gem5::RiscvISA::_rvk_emu_srl_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 126 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_32(), _rvk_emu_ror_32(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), and _rvk_emu_sha512sum1r().

_rvk_emu_srl_64()

int64_t gem5::RiscvISA::_rvk_emu_srl_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 130 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_64(), _rvk_emu_ror_64(), _rvk_emu_sha512sig0(), and _rvk_emu_sha512sig1().

_rvk_emu_unshfl_32()

int32_t gem5::RiscvISA::_rvk_emu_unshfl_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 209 of file rvk.hh.

References _rvk_emu_shuffle32_stage(), rs1, rs2, and x.

Referenced by _rvk_emu_unzip_32().

_rvk_emu_unzip_32()

int32_t gem5::RiscvISA::_rvk_emu_unzip_32 ( int32_t rs1 )

inline

Definition at line 225 of file rvk.hh.

References _rvk_emu_unshfl_32(), and rs1.

_rvk_emu_xperm32()

uint32_t gem5::RiscvISA::_rvk_emu_xperm32 ( uint32_t rs1, uint32_t rs2, int sz_log2 )

inline

Definition at line 272 of file rvk.hh.

References i, mask, r, rs1, and rs2.

Referenced by _rvk_emu_xperm4_32(), and _rvk_emu_xperm8_32().

_rvk_emu_xperm4_32()

int32_t gem5::RiscvISA::_rvk_emu_xperm4_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 285 of file rvk.hh.

References _rvk_emu_xperm32(), rs1, and rs2.

_rvk_emu_xperm4_64()

int64_t gem5::RiscvISA::_rvk_emu_xperm4_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 304 of file rvk.hh.

References _rvk_emu_xperm64(), rs1, and rs2.

_rvk_emu_xperm64()

uint64_t gem5::RiscvISA::_rvk_emu_xperm64 ( uint64_t rs1, uint64_t rs2, int sz_log2 )

inline

Definition at line 291 of file rvk.hh.

References i, mask, r, rs1, and rs2.

Referenced by _rvk_emu_xperm4_64(), and _rvk_emu_xperm8_64().

_rvk_emu_xperm8_32()

int32_t gem5::RiscvISA::_rvk_emu_xperm8_32 ( int32_t rs1, int32_t rs2 )

inline

Definition at line 288 of file rvk.hh.

References _rvk_emu_xperm32(), rs1, and rs2.

_rvk_emu_xperm8_64()

int64_t gem5::RiscvISA::_rvk_emu_xperm8_64 ( int64_t rs1, int64_t rs2 )

inline

Definition at line 307 of file rvk.hh.

References _rvk_emu_xperm64(), rs1, and rs2.

_rvk_emu_zip_32()

int32_t gem5::RiscvISA::_rvk_emu_zip_32 ( int32_t rs1 )

inline

Definition at line 222 of file rvk.hh.

References _rvk_emu_shfl_32(), and rs1.

BitUnion32()

gem5::RiscvISA::BitUnion32

(

IndexReg

)

References p.

Referenced by EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), and EndBitUnion().

BitUnion64() [1/5]

gem5::RiscvISA::BitUnion64

(

ExtMachInst

)

BitUnion64() [2/5]

gem5::RiscvISA::BitUnion64

(

PTESv39

)

References gem5::ArmISA::n.

BitUnion64() [3/5]

gem5::RiscvISA::BitUnion64

(

SATP

)

Referenced by EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), and EndBitUnion().

BitUnion64() [4/5]

gem5::RiscvISA::BitUnion64

(

STATUS

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.

in Figure 3.7. The main register that uses these fields is the MSTATUS register, which is shadowed by two others accessible at lower privilege levels (SSTATUS and USTATUS) that can't see the fields for higher privileges.

BitUnion64() [5/5]

gem5::RiscvISA::BitUnion64

(

VTYPE

)

References vill.

boxF16()

constexpr uint64_t gem5::RiscvISA::boxF16 ( uint16_t v )

staticconstexpr

Definition at line 93 of file float.hh.

References mask, and v.

Referenced by freg().

boxF32()

constexpr uint64_t gem5::RiscvISA::boxF32 ( uint32_t v )

staticconstexpr

Definition at line 94 of file float.hh.

References mask, and v.

Referenced by freg().

checked_vtype()

uint8_t gem5::RiscvISA::checked_vtype ( bool vill, uint8_t vtype )

inline

Definition at line 102 of file vector.hh.

References gem5::bits(), panic_if, vill, vlmul, and vsew.

cpumask_and()

void gem5::RiscvISA::cpumask_and ( RiscvLinux::cpumask_t * dstp, const RiscvLinux::cpumask_t * src1p, const RiscvLinux::cpumask_t * src2p )

inlinestatic

Definition at line 163 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, i, and gem5::RiscvLinux::cpumask::size.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

cpumask_clear()

void gem5::RiscvISA::cpumask_clear ( RiscvLinux::cpumask_t * dstp )

inlinestatic

Definition at line 192 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, and gem5::RiscvLinux::cpumask::size.

Referenced by cpumask_malloc().

cpumask_clear_cpu()

void gem5::RiscvISA::cpumask_clear_cpu ( unsigned int cpu, RiscvLinux::cpumask_t * dstp )

inlinestatic

Definition at line 148 of file se_workload.cc.

References gem5::bits(), gem5::RiscvLinux::cpumask::bits, and gem5::insertBits().

Referenced by hwprobe_get_cpus().

cpumask_copy()

void gem5::RiscvISA::cpumask_copy ( RiscvLinux::cpumask_t * dstp, const RiscvLinux::cpumask_t * srcp )

inlinestatic

Definition at line 185 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, and gem5::RiscvLinux::cpumask::size.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

cpumask_empty()

bool gem5::RiscvISA::cpumask_empty ( const RiscvLinux::cpumask_t * dstp )

inlinestatic

Definition at line 174 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, i, and gem5::RiscvLinux::cpumask::size.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

cpumask_free()

void gem5::RiscvISA::cpumask_free ( RiscvLinux::cpumask_t * cpu_online_mask )

inlinestatic

Definition at line 215 of file se_workload.cc.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

cpumask_malloc()

RiscvLinux::cpumask_t * gem5::RiscvISA::cpumask_malloc ( ThreadContext * tc )

inlinestatic

Definition at line 198 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, cpumask_clear(), gem5::ThreadContext::getSystemPtr(), and gem5::RiscvLinux::cpumask::size.

Referenced by get_cpu_online_mask(), hwprobe_get_cpus(), and hwprobe_get_values().

cpumask_set_cpu()

void gem5::RiscvISA::cpumask_set_cpu ( unsigned int cpu, RiscvLinux::cpumask_t * dstp )

inlinestatic

Definition at line 140 of file se_workload.cc.

References gem5::bits(), gem5::RiscvLinux::cpumask::bits, and gem5::insertBits().

Referenced by get_cpu_online_mask(), and hwprobe_get_cpus().

cpumask_test_cpu()

bool gem5::RiscvISA::cpumask_test_cpu ( unsigned int cpu, const RiscvLinux::cpumask_t * cpumask )

inlinestatic

Definition at line 156 of file se_workload.cc.

References gem5::bits(), and gem5::RiscvLinux::cpumask::bits.

Referenced by hwprobe_get_cpus().

div()

template<typename T>

T gem5::RiscvISA::div ( T rs1, T rs2 )

inline

Definition at line 192 of file utility.hh.

References rs1, and rs2.

Referenced by gem5::free_bsd::onUDelay(), gem5::linux::onUDelay(), gem5::printSize(), gem5::ClockRateControlFwIf::set_mul_div(), gem5::free_bsd::SkipUDelay< ABI, Base >::SkipUDelay(), and gem5::linux::SkipUDelay< ABI, Base >::SkipUDelay().

divu()

template<typename T>

T gem5::RiscvISA::divu ( T rs1, T rs2 )

inline

Definition at line 205 of file utility.hh.

References rs1, and rs2.

elem_mask()

template<typename T>

int gem5::RiscvISA::elem_mask ( const T * vs, const int index )

inline

Definition at line 307 of file utility.hh.

References index, and vs.

Referenced by gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::getElem(), and gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::setElem().

elem_mask_vseg()

template<typename T>

int gem5::RiscvISA::elem_mask_vseg ( const T * vs, const int elem, const int num_fields )

inline

Definition at line 317 of file utility.hh.

References index, and vs.

EndBitUnion() [1/34]

gem5::RiscvISA::EndBitUnion

(

CacheErrReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [2/34]

gem5::RiscvISA::EndBitUnion

(

CauseReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [3/34]

gem5::RiscvISA::EndBitUnion

(

Config1Reg

)

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

EndBitUnion() [4/34]

gem5::RiscvISA::EndBitUnion

(

Config2Reg

)

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

EndBitUnion() [5/34]

gem5::RiscvISA::EndBitUnion

(

Config3Reg

)

References BitUnion64(), and EndBitUnion().

EndBitUnion() [6/34]

gem5::RiscvISA::EndBitUnion

(

ConfigReg

)

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

EndBitUnion() [7/34]

gem5::RiscvISA::EndBitUnion

(

ContextReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [8/34]

gem5::RiscvISA::EndBitUnion

(

EBaseReg

)

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

EndBitUnion() [9/34]

gem5::RiscvISA::EndBitUnion

(

EntryHiReg

)

References BitUnion32(), EndBitUnion(), and SubBitUnion().

EndBitUnion() [10/34]

gem5::RiscvISA::EndBitUnion

(

EntryLoReg

)

References BitUnion64(), and EndBitUnion().

EndBitUnion() [11/34]

gem5::RiscvISA::EndBitUnion

(

ExtMachInst

)

const

References EndBitUnion().

EndBitUnion() [12/34]

gem5::RiscvISA::EndBitUnion

(

HSTATUS

)

These fields are specified in the RISC-V Instruction Set Manual.

Resumable Non-Maskable Interrupts. The main register that uses these fields is the MNSTATUS register

References BitUnion64(), and EndBitUnion().

EndBitUnion() [13/34]

gem5::RiscvISA::EndBitUnion

(

HWREnaReg

)

References BitUnion64(), EndBitUnion(), fill, and r.

EndBitUnion() [14/34]

gem5::RiscvISA::EndBitUnion

(

IndexReg

)

EndBitUnion() [15/34]

gem5::RiscvISA::EndBitUnion

(

IntCtlReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [16/34]

gem5::RiscvISA::EndBitUnion

(

INTERRUPT

)

References BitUnion64(), EndBitUnion(), and INTERRUPT.

EndBitUnion() [17/34]

gem5::RiscvISA::EndBitUnion

(

JVT

)

const

Definition at line 1455 of file misc.hh.

References EndBitUnion(), RV32, and RV64.

EndBitUnion() [18/34]

gem5::RiscvISA::EndBitUnion

(

MISA

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.

Both the MIP and MIE registers have the same fields, so accesses to either should use this bit union.

References BitUnion64(), EndBitUnion(), and INTERRUPT.

EndBitUnion() [19/34]

gem5::RiscvISA::EndBitUnion

(

NSTATUS

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org.

The register is used to control instruction extensions.

References BitUnion64(), and EndBitUnion().

EndBitUnion() [20/34]

gem5::RiscvISA::EndBitUnion

(

PageGrainReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [21/34]

gem5::RiscvISA::EndBitUnion

(

PageMaskReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [22/34]

gem5::RiscvISA::EndBitUnion

(

PerfCntCtlReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [23/34]

gem5::RiscvISA::EndBitUnion

(

PRIdReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [24/34]

gem5::RiscvISA::EndBitUnion

(

PTESv39

)

Remove the page offset and the upper bits that are not part of the VPN from the address.

Note that this must assume the smallest page size

References mode, and vaddr.

EndBitUnion() [25/34]

gem5::RiscvISA::EndBitUnion

(

RandomReg

)

References BitUnion64(), and EndBitUnion().

EndBitUnion() [26/34]

gem5::RiscvISA::EndBitUnion

(

SATP

)

Definition at line 49 of file pagetable.hh.

References EndBitUnion().

Referenced by EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), EndBitUnion(), and EndBitUnion().

EndBitUnion() [27/34]

gem5::RiscvISA::EndBitUnion

(

SENVCFG

)

References BitUnion64(), and EndBitUnion().

EndBitUnion() [28/34]

gem5::RiscvISA::EndBitUnion

(

SRSCtlReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [29/34]

gem5::RiscvISA::EndBitUnion

(

SRSMapReg

)

References gem5::PowerISA::bd, BitUnion32(), and EndBitUnion().

EndBitUnion() [30/34]

gem5::RiscvISA::EndBitUnion

(

STATUS

)

EndBitUnion() [31/34]

gem5::RiscvISA::EndBitUnion

(

StatusReg

)

References BitUnion32(), and EndBitUnion().

EndBitUnion() [32/34]

gem5::RiscvISA::EndBitUnion

(

WatchHiReg

)

References BitUnion32(), EndBitUnion(), gem5::ArmISA::m, and w.

EndBitUnion() [33/34]

gem5::RiscvISA::EndBitUnion

(

WatchLoReg

)

References asid, BitUnion32(), EndBitUnion(), g, i, gem5::ArmISA::m, mask, r, and w.

EndBitUnion() [34/34]

gem5::RiscvISA::EndBitUnion

(

WiredReg

)

References BitUnion32(), and EndBitUnion().

EndSubBitUnion() [1/4]

gem5::RiscvISA::EndSubBitUnion

(

cu

)

References EndSubBitUnion().

Referenced by EndSubBitUnion(), EndSubBitUnion(), EndSubBitUnion(), and EndSubBitUnion().

EndSubBitUnion() [2/4]

gem5::RiscvISA::EndSubBitUnion

(

im

)

References EndSubBitUnion().

EndSubBitUnion() [3/4]

gem5::RiscvISA::EndSubBitUnion

(

ip

)

References EndSubBitUnion().

EndSubBitUnion() [4/4]

gem5::RiscvISA::EndSubBitUnion

(

vtype8

)

References EndSubBitUnion(), gem5::ArmISA::instBits, and vtype8.

f16() [1/2]

constexpr float16_t gem5::RiscvISA::f16 ( freg_t r )

staticconstexpr

Definition at line 100 of file float.hh.

References r, and unboxF16().

f16() [2/2]

constexpr float16_t gem5::RiscvISA::f16 ( uint16_t v )

staticconstexpr

Definition at line 97 of file float.hh.

References v.

Referenced by fclassify(), fneg(), fsgnj16(), ftype(), and ftype_freg().

f32() [1/2]

constexpr float32_t gem5::RiscvISA::f32 ( freg_t r )

staticconstexpr

Definition at line 101 of file float.hh.

References r, and unboxF32().

f32() [2/2]

constexpr float32_t gem5::RiscvISA::f32 ( uint32_t v )

staticconstexpr

Definition at line 98 of file float.hh.

References v.

Referenced by fclassify(), fneg(), fsgnj32(), ftype(), and ftype_freg().

f64() [1/2]

constexpr float64_t gem5::RiscvISA::f64 ( freg_t r )

staticconstexpr

Definition at line 102 of file float.hh.

References r.

f64() [2/2]

constexpr float64_t gem5::RiscvISA::f64 ( uint64_t v )

staticconstexpr

Definition at line 99 of file float.hh.

References v.

Referenced by fclassify(), fneg(), fsgnj64(), ftype(), and ftype_freg().

f_to_i()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

IntType gem5::RiscvISA::f_to_i	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 595 of file utility.hh.

References a, and mode.

f_to_nf()

template<typename FloatNType, typename FloatType = typename double_width<FloatNType>::type>

FloatNType gem5::RiscvISA::f_to_nf

(

FloatType

a

)

Definition at line 735 of file utility.hh.

References a.

f_to_ni()

template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>

IntType gem5::RiscvISA::f_to_ni	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 623 of file utility.hh.

References a, and mode.

f_to_nui()

template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>

IntType gem5::RiscvISA::f_to_nui	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 583 of file utility.hh.

References a, and mode.

f_to_ui()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

IntType gem5::RiscvISA::f_to_ui	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 555 of file utility.hh.

References a, and mode.

f_to_wf()

template<typename FloatType, typename FloatWType = typename double_width<FloatType>::type>

FloatWType gem5::RiscvISA::f_to_wf

(

FloatType

a

)

Definition at line 722 of file utility.hh.

References a.

f_to_wi()

template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>

IntType gem5::RiscvISA::f_to_wi	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 610 of file utility.hh.

References a, and mode.

f_to_wui()

template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>

IntType gem5::RiscvISA::f_to_wui	(	FloatType	a,
		uint_fast8_t	mode )

Definition at line 570 of file utility.hh.

References a, and mode.

fadd()

template<typename FloatType>

FloatType gem5::RiscvISA::fadd	(	FloatType	a,
		FloatType	b )

Definition at line 353 of file utility.hh.

References a, and gem5::ArmISA::b.

fclassify()

template<typename FloatType>

FloatType gem5::RiscvISA::fclassify

(

FloatType

a

)

Definition at line 461 of file utility.hh.

References a, f16(), f32(), and f64().

fdiv()

template<typename FloatType>

FloatType gem5::RiscvISA::fdiv	(	FloatType	a,
		FloatType	b )

Definition at line 401 of file utility.hh.

References a, and gem5::ArmISA::b.

feq()

template<typename FloatType>

bool gem5::RiscvISA::feq	(	FloatType	a,
		FloatType	b )

Definition at line 497 of file utility.hh.

References a, and gem5::ArmISA::b.

fle()

template<typename FloatType>

bool gem5::RiscvISA::fle	(	FloatType	a,
		FloatType	b )

Definition at line 485 of file utility.hh.

References a, and gem5::ArmISA::b.

floatRegClass()

RegClass gem5::RiscvISA::floatRegClass ( FloatRegClass , FloatRegClassName , float_reg::NumRegs , debug::FloatRegs  )

inlineconstexpr

References gem5::FloatRegClass, gem5::FloatRegClassName, and gem5::RiscvISA::float_reg::NumRegs.

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::RiscvISA::ISA::ISA(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), and gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs().

flt()

template<typename FloatType>

bool gem5::RiscvISA::flt	(	FloatType	a,
		FloatType	b )

Definition at line 509 of file utility.hh.

References a, and gem5::ArmISA::b.

Referenced by gem5::ruby::garnet::flitBuffer::insert().

fmadd()

template<typename FloatType>

FloatType gem5::RiscvISA::fmadd	(	FloatType	a,
		FloatType	b,
		FloatType	c )

Definition at line 521 of file utility.hh.

References a, gem5::ArmISA::b, and c.

fmax()

template<typename FloatType>

FloatType gem5::RiscvISA::fmax	(	FloatType	a,
		FloatType	b )

Definition at line 389 of file utility.hh.

References a, and gem5::ArmISA::b.

Referenced by gem5::ArmISA::fpMaxNum(), and gem5::RealViewTemperatureSensor::read().

fmin()

template<typename FloatType>

FloatType gem5::RiscvISA::fmin	(	FloatType	a,
		FloatType	b )

Definition at line 377 of file utility.hh.

References a, and gem5::ArmISA::b.

Referenced by gem5::ArmISA::fpMinNum().

fmul()

template<typename FloatType>

FloatType gem5::RiscvISA::fmul	(	FloatType	a,
		FloatType	b )

Definition at line 413 of file utility.hh.

References a, and gem5::ArmISA::b.

fneg()

template<typename FloatType>

FloatType gem5::RiscvISA::fneg

(

FloatType

a

)

Definition at line 533 of file utility.hh.

References a, f16(), f32(), f64(), and mask.

frecip7()

template<typename FloatType>

FloatType gem5::RiscvISA::frecip7

(

FloatType

a

)

Definition at line 449 of file utility.hh.

References a.

freg() [1/4]

constexpr freg_t gem5::RiscvISA::freg ( float16_t f )

staticconstexpr

Definition at line 105 of file float.hh.

References boxF16(), and gem5::ArmISA::f.

freg() [2/4]

constexpr freg_t gem5::RiscvISA::freg ( float32_t f )

staticconstexpr

Definition at line 106 of file float.hh.

References boxF32(), and gem5::ArmISA::f.

freg() [3/4]

constexpr freg_t gem5::RiscvISA::freg ( float64_t f )

staticconstexpr

Definition at line 107 of file float.hh.

References gem5::ArmISA::f.

freg() [4/4]

constexpr freg_t gem5::RiscvISA::freg ( uint_fast64_t f )

staticconstexpr

Definition at line 108 of file float.hh.

References gem5::ArmISA::f.

frsqrte7()

template<typename FloatType>

FloatType gem5::RiscvISA::frsqrte7

(

FloatType

a

)

Definition at line 437 of file utility.hh.

References a.

fsgnj()

template<typename FloatType>

FloatType gem5::RiscvISA::fsgnj	(	FloatType	a,
		FloatType	b,
		bool	n,
		bool	x )

Definition at line 473 of file utility.hh.

References a, gem5::ArmISA::b, fsgnj16(), fsgnj32(), fsgnj64(), gem5::ArmISA::n, and x.

fsgnj16()

float16_t gem5::RiscvISA::fsgnj16 ( float16_t a, float16_t b, bool n, bool x )

inline

Definition at line 219 of file float.hh.

References a, gem5::ArmISA::b, f16(), gem5::insertBits(), gem5::ArmISA::n, and x.

Referenced by fsgnj().

fsgnj32()

float32_t gem5::RiscvISA::fsgnj32 ( float32_t a, float32_t b, bool n, bool x )

inline

Definition at line 226 of file float.hh.

References a, gem5::ArmISA::b, f32(), gem5::insertBits(), gem5::ArmISA::n, and x.

Referenced by fsgnj().

fsgnj64()

float64_t gem5::RiscvISA::fsgnj64 ( float64_t a, float64_t b, bool n, bool x )

inline

Definition at line 233 of file float.hh.

References a, gem5::ArmISA::b, f64(), gem5::insertBits(), gem5::ArmISA::n, and x.

Referenced by fsgnj().

fsqrt()

template<typename FloatType>

FloatType gem5::RiscvISA::fsqrt

(

FloatType

a

)

Definition at line 425 of file utility.hh.

References a.

fsub()

template<typename FloatType>

FloatType gem5::RiscvISA::fsub	(	FloatType	a,
		FloatType	b )

Definition at line 365 of file utility.hh.

References a, and gem5::ArmISA::b.

ftype()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

auto gem5::RiscvISA::ftype

(

IntType

a

)

-> FloatType

Definition at line 327 of file utility.hh.

References a, f16(), f32(), and f64().

ftype_freg()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

auto gem5::RiscvISA::ftype_freg

(

freg_t

a

)

-> FloatType

Definition at line 341 of file utility.hh.

References a, f16(), f32(), and f64().

fwiden()

template<typename FT, typename WFT = typename double_width<FT>::type>

WFT gem5::RiscvISA::fwiden

(

FT

a

)

Definition at line 545 of file utility.hh.

References a.

get_cpu_online_mask()

RiscvLinux::cpumask_t * gem5::RiscvISA::get_cpu_online_mask ( ThreadContext * tc )

inlinestatic

Definition at line 255 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, cpumask_malloc(), cpumask_set_cpu(), gem5::ThreadContext::getSystemPtr(), and i.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

get_emul()

uint32_t gem5::RiscvISA::get_emul ( uint32_t eew, uint32_t sew, float vflmul, bool is_mask_ldst )

inline

Definition at line 62 of file vector.hh.

getFaultVAddr()

bool gem5::RiscvISA::getFaultVAddr	(	Fault	fault,
		Addr &	va )

Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.

If true it is storing the faulting address in the va argument

Parameters

fault	generated fault
va	function will modify this passed-by-reference parameter with the correct faulting virtual address

Returns

true if va contains a valid value, false otherwise

Definition at line 337 of file faults.cc.

References gem5::ArmISA::va.

getSew()

uint32_t gem5::RiscvISA::getSew ( uint32_t vsew )

inline

Definition at line 52 of file vector.hh.

References vsew.

Referenced by getVlmax().

getVflmul()

float gem5::RiscvISA::getVflmul

(

uint32_t

vlmul_encoding

)

This function translates the 3-bit value of vlmul bits to the corresponding lmul value as specified in RVV 1.0 spec p11-12 chapter 3.4.2.

I.e., vlmul = -3 -> LMUL = 1/8 vlmul = -2 -> LMUL = 1/4 vlmul = -1 -> LMUL = 1/2 vlmul = 0 -> LMUL = 1 vlmul = 1 -> LMUL = 2 vlmul = 2 -> LMUL = 4 vlmul = 3 -> LMUL = 8

Definition at line 62 of file vector.cc.

References gem5::sext(), and vlmul.

Referenced by getVlmax().

getVlmax()

uint32_t gem5::RiscvISA::getVlmax	(	VTYPE	vtype,
		uint32_t	vlen )

Definition at line 70 of file vector.cc.

References getSew(), and getVflmul().

getVPNFromVAddr()

Addr gem5::RiscvISA::getVPNFromVAddr	(	Addr	vaddr,
		Addr	mode )

Definition at line 64 of file pagetable.cc.

References gem5::bits(), mode, panic, and vaddr.

Referenced by gem5::RiscvISA::TLB::doTranslate(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::Walker::startWalkWrapper(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalkGStage(), and gem5::RiscvISA::Walker::WalkerState::walkTwoStage().

hwprobe_get_cpus()

template<class OS>

int gem5::RiscvISA::hwprobe_get_cpus ( ThreadContext * tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags )

static

Definition at line 428 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), cpumask_and(), cpumask_clear_cpu(), cpumask_copy(), cpumask_empty(), cpumask_free(), cpumask_malloc(), cpumask_set_cpu(), cpumask_test_cpu(), get_cpu_online_mask(), hwprobe_one_pair(), i, gem5::RiscvLinux::riscv_hwprobe::key, riscv_hwprobe_key_is_valid(), riscv_hwprobe_pair_cmp(), RISCV_HWPROBE_WHICH_CPUS, and gem5::RiscvLinux::cpumask::size.

Referenced by riscvHWProbeFunc().

hwprobe_get_values()

template<class OS>

int gem5::RiscvISA::hwprobe_get_values ( ThreadContext * tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags )

static

Definition at line 356 of file se_workload.cc.

References gem5::RiscvLinux::cpumask::bits, gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), cpumask_and(), cpumask_copy(), cpumask_empty(), cpumask_free(), cpumask_malloc(), get_cpu_online_mask(), hwprobe_one_pair(), i, gem5::RiscvLinux::cpumask::size, and gem5::RiscvLinux::riscv_hwprobe::value.

Referenced by riscvHWProbeFunc().

hwprobe_key_is_bitmask()

bool gem5::RiscvISA::hwprobe_key_is_bitmask ( int64_t key )

inlinestatic

Definition at line 227 of file se_workload.cc.

References gem5::RiscvLinux::BaseBehavior, gem5::RiscvLinux::Cpuperf0, and gem5::RiscvLinux::IMAExt0.

Referenced by riscv_hwprobe_pair_cmp().

hwprobe_one_pair()

void gem5::RiscvISA::hwprobe_one_pair ( ThreadContext * tc, RiscvLinux::riscv_hwprobe * pair, RiscvLinux::cpumask_t * cpus )

static

Definition at line 275 of file se_workload.cc.

References gem5::RiscvLinux::BaseBehavior, gem5::System::cacheLineSize(), gem5::RiscvLinux::Cpuperf0, CSR_MARCHID, CSR_MIMPID, CSR_MVENDORID, CSRData, gem5::ArmISA::ext, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::RiscvLinux::HighestVirtAddress, gem5::RiscvLinux::IMAExt0, gem5::RiscvLinux::riscv_hwprobe::key, gem5::RiscvLinux::Marchid, gem5::Process::memState, gem5::RiscvLinux::Mimpid, gem5::RiscvLinux::MisalignedScalarPerf, MISCREG_ISA, gem5::RiscvLinux::Mvendorid, gem5::ThreadContext::readMiscRegNoEffect(), gem5::RiscvLinux::riscv_hwprobe::value, and gem5::RiscvLinux::ZicbozBlockSize.

Referenced by hwprobe_get_cpus(), and hwprobe_get_values().

i_to_f()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

FloatType gem5::RiscvISA::i_to_f

(

IntType

a

)

Definition at line 677 of file utility.hh.

References a.

i_to_nf()

template<typename FloatType, typename IntType = std::make_signed_t< decltype(double_width<FloatType>::type::v) >>

FloatType gem5::RiscvISA::i_to_nf

(

IntType

a

)

Definition at line 709 of file utility.hh.

References a.

i_to_wf()

template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>

FloatType gem5::RiscvISA::i_to_wf

(

IntType

a

)

Definition at line 692 of file utility.hh.

References a.

int_rounding()

template<typename T>

T gem5::RiscvISA::int_rounding	(	T	result,
		uint8_t	xrm,
		unsigned	gb )

Ref: https://github.com/riscv-software-src/riscv-isa-sim.

Definition at line 817 of file utility.hh.

References panic.

intRegClass()

RegClass gem5::RiscvISA::intRegClass ( IntRegClass , IntRegClassName , int_reg::NumRegs , debug::IntRegs  )

inlineconstexpr

References gem5::IntRegClass, gem5::IntRegClassName, and gem5::RiscvISA::int_reg::NumRegs.

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::RiscvISA::ISA::ISA(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), and gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs().

isaExtsFlags() [1/2]

uint64_t gem5::RiscvISA::isaExtsFlags ( )

constexpr

Definition at line 600 of file misc.hh.

isaExtsFlags() [2/2]

template<typename... T>

uint64_t gem5::RiscvISA::isaExtsFlags ( T... isa_exts )

constexpr

Definition at line 596 of file misc.hh.

isquietnan()

template<typename T>

bool gem5::RiscvISA::isquietnan ( T val )

inline

Definition at line 90 of file utility.hh.

References gem5::X86ISA::val.

isquietnan< double >()

template<>

bool gem5::RiscvISA::isquietnan< double > ( double val )

inline

Definition at line 102 of file utility.hh.

References std::isnan(), and gem5::X86ISA::val.

isquietnan< float >()

template<>

bool gem5::RiscvISA::isquietnan< float > ( float val )

inline

Definition at line 95 of file utility.hh.

References std::isnan(), and gem5::X86ISA::val.

issignalingnan()

template<typename T>

bool gem5::RiscvISA::issignalingnan ( T val )

inline

Definition at line 110 of file utility.hh.

References gem5::X86ISA::val.

issignalingnan< double >()

template<>

bool gem5::RiscvISA::issignalingnan< double > ( double val )

inline

Definition at line 122 of file utility.hh.

References std::isnan(), and gem5::X86ISA::val.

issignalingnan< float >()

template<>

bool gem5::RiscvISA::issignalingnan< float > ( float val )

inline

Definition at line 115 of file utility.hh.

References std::isnan(), and gem5::X86ISA::val.

miscRegClass()

RegClass gem5::RiscvISA::miscRegClass ( MiscRegClass , MiscRegClassName , NUM_MISCREGS , debug::MiscRegs  )

inlineconstexpr

References gem5::MiscRegClass, gem5::MiscRegClassName, and NUM_MISCREGS.

Referenced by gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), and gem5::RiscvISA::ISA::ISA().

mulh()

template<typename T>

std::make_signed_t< T > gem5::RiscvISA::mulh ( std::make_signed_t< T > rs1, std::make_signed_t< T > rs2 )

inline

Definition at line 178 of file utility.hh.

References rs1, and rs2.

mulhsu()

template<typename T>

std::make_signed_t< T > gem5::RiscvISA::mulhsu ( std::make_signed_t< T > rs1, std::make_unsigned_t< T > rs2 )

inline

Definition at line 185 of file utility.hh.

References rs1, and rs2.

mulhu()

template<typename T>

std::make_unsigned_t< T > gem5::RiscvISA::mulhu ( std::make_unsigned_t< T > rs1, std::make_unsigned_t< T > rs2 )

inline

Definition at line 171 of file utility.hh.

References rs1, and rs2.

registerName()

std::string gem5::RiscvISA::registerName ( RegId reg )

inline

Definition at line 130 of file utility.hh.

References gem5::FloatRegClass, gem5::IntRegClass, gem5::RiscvISA::int_reg::NumArchRegs, gem5::RiscvISA::float_reg::NumRegs, NumVecRegs, gem5::X86ISA::reg, gem5::RiscvISA::float_reg::RegNames, gem5::RiscvISA::int_reg::RegNames, gem5::VecRegClass, and VecRegNames.

Referenced by gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly(), gem5::RiscvISA::BSOp::generateDisassembly(), gem5::RiscvISA::CompRegOp::generateDisassembly(), gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::Load::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::LoadReservedMicro::generateDisassembly(), gem5::RiscvISA::RegOp::generateDisassembly(), gem5::RiscvISA::Store::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::StoreCondMicro::generateDisassembly(), gem5::RiscvISA::SystemOp::generateDisassembly(), gem5::RiscvISA::VConfOp::generateDisassembly(), gem5::RiscvISA::VCpyVsMicroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMacroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMicroInst::generateDisassembly(), gem5::RiscvISA::VectorNonSplitInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMacroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMicroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MacroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MicroInst::generateDisassembly(), gem5::RiscvISA::VlElementMacroInst::generateDisassembly(), gem5::RiscvISA::VlElementMicroInst::generateDisassembly(), gem5::RiscvISA::VleMacroInst::generateDisassembly(), gem5::RiscvISA::VleMicroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegMacroInst::generateDisassembly(), gem5::RiscvISA::VlSegMicroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VMaskMergeMicroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VPinVdMicroInst::generateDisassembly(), gem5::RiscvISA::VsElementMacroInst::generateDisassembly(), gem5::RiscvISA::VsElementMicroInst::generateDisassembly(), gem5::RiscvISA::VseMacroInst::generateDisassembly(), gem5::RiscvISA::VseMicroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegMacroInst::generateDisassembly(), gem5::RiscvISA::VsSegMicroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMicroInst::generateDisassembly(), and gem5::RiscvISA::CmMacroInst::getRlistStr().

rem()

template<typename T>

T gem5::RiscvISA::rem ( T rs1, T rs2 )

inline

Definition at line 215 of file utility.hh.

References rs1, and rs2.

remu()

template<typename T>

T gem5::RiscvISA::remu ( T rs1, T rs2 )

inline

Definition at line 228 of file utility.hh.

References rs1, and rs2.

resetV() [1/2]

void gem5::RiscvISA::resetV

(

ExecContext *

xc

)

Definition at line 1347 of file isa.cc.

References MISCREG_VIRT, gem5::ExecContext::setMiscReg(), and virtualizationEnabled().

Referenced by gem5::RiscvISA::RiscvFault::invoke().

resetV() [2/2]

void gem5::RiscvISA::resetV

(

ThreadContext *

tc

)

Definition at line 1351 of file isa.cc.

References MISCREG_VIRT, gem5::ThreadContext::setMiscReg(), and virtualizationEnabled().

riscv_hwprobe_key_is_valid()

bool gem5::RiscvISA::riscv_hwprobe_key_is_valid ( int64_t key )

inlinestatic

Definition at line 221 of file se_workload.cc.

References RISCV_HWPROBE_MAX_KEY.

Referenced by hwprobe_get_cpus().

riscv_hwprobe_pair_cmp()

bool gem5::RiscvISA::riscv_hwprobe_pair_cmp ( RiscvLinux::riscv_hwprobe * pair, RiscvLinux::riscv_hwprobe * other_pair )

inlinestatic

Definition at line 240 of file se_workload.cc.

References hwprobe_key_is_bitmask(), gem5::RiscvLinux::riscv_hwprobe::key, and gem5::RiscvLinux::riscv_hwprobe::value.

Referenced by hwprobe_get_cpus().

riscvHWProbeFunc()

template<class OS>

SyscallReturn gem5::RiscvISA::riscvHWProbeFunc ( SyscallDesc * desc, ThreadContext * tc, VPtr<> pairs, typename OS::size_t pair_count, typename OS::size_t cpusetsize, VPtr<> cpus_user, unsigned int flags )

static

Definition at line 516 of file se_workload.cc.

References hwprobe_get_cpus(), hwprobe_get_values(), and RISCV_HWPROBE_WHICH_CPUS.

rvTypeFlags()

template<typename... T>

uint64_t gem5::RiscvISA::rvTypeFlags ( T... args )

constexpr

Definition at line 591 of file misc.hh.

sat_add()

template<typename T>

T gem5::RiscvISA::sat_add	(	T	x,
		T	y,
		bool *	sat )

Definition at line 746 of file utility.hh.

References gem5::ArmISA::sh, ux, and x.

sat_addu()

template<typename T>

T gem5::RiscvISA::sat_addu	(	T	x,
		T	y,
		bool *	sat )

Definition at line 784 of file utility.hh.

References gem5::ArmISA::t, and x.

sat_sub()

template<typename T>

T gem5::RiscvISA::sat_sub	(	T	x,
		T	y,
		bool *	sat )

Definition at line 765 of file utility.hh.

References gem5::ArmISA::sh, ux, and x.

sat_subu()

template<typename T>

T gem5::RiscvISA::sat_subu	(	T	x,
		T	y,
		bool *	sat )

Definition at line 798 of file utility.hh.

References gem5::ArmISA::t, and x.

setV() [1/2]

void gem5::RiscvISA::setV

(

ExecContext *

xc

)

Definition at line 1338 of file isa.cc.

References MISCREG_VIRT, gem5::ExecContext::setMiscReg(), and virtualizationEnabled().

setV() [2/2]

void gem5::RiscvISA::setV

(

ThreadContext *

tc

)

Definition at line 1342 of file isa.cc.

References MISCREG_VIRT, gem5::ThreadContext::setMiscReg(), and virtualizationEnabled().

SubBitUnion() [1/3]

gem5::RiscvISA::SubBitUnion	(	im	,
		15	,
		8	)

References SubBitUnion().

Referenced by EndBitUnion(), SubBitUnion(), SubBitUnion(), and SubBitUnion().

SubBitUnion() [2/3]

gem5::RiscvISA::SubBitUnion	(	ip	,
		15	,
		8	)

References SubBitUnion().

SubBitUnion() [3/3]

gem5::RiscvISA::SubBitUnion	(	vtype8	,
		39	,
		32	)

References SubBitUnion(), vlmul, vma, vsew, vta, and vtype8.

ui_to_f()

template<typename FloatType, typename IntType = decltype(FloatType::v)>

FloatType gem5::RiscvISA::ui_to_f

(

IntType

a

)

Definition at line 636 of file utility.hh.

References a.

ui_to_nf()

template<typename FloatType, typename IntType = decltype(double_width<FloatType>::type::v)>

FloatType gem5::RiscvISA::ui_to_nf

(

IntType

a

)

Definition at line 666 of file utility.hh.

References a.

ui_to_wf()

template<typename IntType, typename FloatType = typename double_widthf<IntType>::type>

FloatType gem5::RiscvISA::ui_to_wf

(

IntType

a

)

Definition at line 651 of file utility.hh.

References a.

unameFunc32()

SyscallReturn gem5::RiscvISA::unameFunc32 ( SyscallDesc * desc, ThreadContext * tc, VPtr< Linux::utsname > name )

static

Target uname() handler.

Definition at line 126 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

unameFunc64()

SyscallReturn gem5::RiscvISA::unameFunc64 ( SyscallDesc * desc, ThreadContext * tc, VPtr< Linux::utsname > name )

static

Target uname() handler.

Definition at line 111 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

unboxF16()

constexpr uint16_t gem5::RiscvISA::unboxF16 ( uint64_t v )

staticconstexpr

Definition at line 73 of file float.hh.

References gem5::bits(), mask, and v.

Referenced by f16().

unboxF32()

constexpr uint32_t gem5::RiscvISA::unboxF32 ( uint64_t v )

staticconstexpr

Definition at line 84 of file float.hh.

References gem5::bits(), mask, and v.

Referenced by f32().

updateFPUStatus()

Fault gem5::RiscvISA::updateFPUStatus	(	ExecContext *	xc,
		ExtMachInst	machInst,
		bool	set_dirty )

Definition at line 1358 of file isa.cc.

References DIRTY, MISCREG_ISA, MISCREG_STATUS, MISCREG_VSSTATUS, gem5::NoFault, OFF, gem5::ExecContext::readMiscReg(), gem5::ExecContext::setMiscReg(), gem5::ArmISA::status, and virtualizationEnabled().

updateVPUStatus()

Fault gem5::RiscvISA::updateVPUStatus	(	ExecContext *	xc,
		ExtMachInst	machInst,
		bool	set_dirty,
		bool	check_vill )

Definition at line 1385 of file isa.cc.

References DIRTY, MISCREG_ISA, MISCREG_STATUS, MISCREG_VSSTATUS, gem5::NoFault, OFF, gem5::ExecContext::readMiscReg(), gem5::ExecContext::setMiscReg(), gem5::ArmISA::status, and virtualizationEnabled().

Referenced by gem5::RiscvISA::VCpyVsMicroInst::execute(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), and gem5::RiscvISA::VPinVdMicroInst::execute().

virtualizationEnabled() [1/2]

bool gem5::RiscvISA::virtualizationEnabled

(

ExecContext *

xc

)

Definition at line 1331 of file isa.cc.

References MISCREG_VIRT, and gem5::ExecContext::readMiscReg().

Referenced by gem5::RiscvISA::SystemOp::executeEBreakOrSemihosting(), gem5::RiscvISA::TLB::getMemAccessInfo(), gem5::RiscvISA::Interrupts::globalMask(), gem5::RiscvISA::RiscvFault::invoke(), resetV(), resetV(), setV(), setV(), updateFPUStatus(), and updateVPUStatus().

virtualizationEnabled() [2/2]

bool gem5::RiscvISA::virtualizationEnabled

(

ThreadContext *

tc

)

Definition at line 1334 of file isa.cc.

References MISCREG_VIRT, and gem5::ThreadContext::readMiscReg().

vtype_regs_per_group()

uint64_t gem5::RiscvISA::vtype_regs_per_group ( const uint64_t vtype )

inline

Definition at line 276 of file utility.hh.

References gem5::bits(), and gem5::sext().

vtype_set_vill()

void gem5::RiscvISA::vtype_set_vill ( uint64_t & vtype )

inline

Definition at line 283 of file utility.hh.

vtype_SEW()

uint64_t gem5::RiscvISA::vtype_SEW ( const uint64_t vtype )

inline

Definition at line 235 of file utility.hh.

References gem5::bits().

vtype_VLMAX()

uint64_t gem5::RiscvISA::vtype_VLMAX ( const uint64_t vtype, const uint64_t vlen, const bool per_reg = false )

inline

Definition at line 260 of file utility.hh.

References gem5::bits(), gem5::sext(), and vsew.

vtype_vlmul()

int64_t gem5::RiscvISA::vtype_vlmul ( const uint64_t vtype )

inline

Definition at line 270 of file utility.hh.

References gem5::bits(), and gem5::sext().

Referenced by gem5::RiscvISA::VectorMacroInst::VectorMacroInst(), and gem5::RiscvISA::VectorMicroInst::VectorMicroInst().

width_EEW()

uint64_t gem5::RiscvISA::width_EEW ( uint64_t width )

inline

Definition at line 289 of file utility.hh.

References width.

Referenced by gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VectorMemMacroInst::VectorMemMacroInst(), and gem5::RiscvISA::VectorMemMicroInst::VectorMemMicroInst().

Variable Documentation

_rvk_emu_aes_fwd_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_aes_fwd_sbox[256]

Initial value:

= {
    0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B,
    0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
    0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26,
    0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
    0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2,
    0xEB, 0x27, 0xB2, 0x75, 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
    0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, 0x53, 0xD1, 0x00, 0xED,
    0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
    0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F,
    0x50, 0x3C, 0x9F, 0xA8, 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
    0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, 0xCD, 0x0C, 0x13, 0xEC,
    0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
    0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14,
    0xDE, 0x5E, 0x0B, 0xDB, 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
    0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, 0xE7, 0xC8, 0x37, 0x6D,
    0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
    0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F,
    0x4B, 0xBD, 0x8B, 0x8A, 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
    0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, 0xE1, 0xF8, 0x98, 0x11,
    0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
    0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F,
    0xB0, 0x54, 0xBB, 0x16
}

Ref: https://github.com/rvkrypto/rvkrypto-fips.

Definition at line 47 of file rvk.hh.

Referenced by _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64es(), and _rvk_emu_aes64ks1i().

_rvk_emu_aes_inv_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_aes_inv_sbox[256]

Initial value:

= {
    0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E,
    0x81, 0xF3, 0xD7, 0xFB, 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
    0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, 0x54, 0x7B, 0x94, 0x32,
    0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
    0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49,
    0x6D, 0x8B, 0xD1, 0x25, 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
    0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, 0x6C, 0x70, 0x48, 0x50,
    0xFD, 0xED, 0xB9, 0xDA, 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
    0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05,
    0xB8, 0xB3, 0x45, 0x06, 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
    0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, 0x3A, 0x91, 0x11, 0x41,
    0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
    0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, 0x37, 0xE8,
    0x1C, 0x75, 0xDF, 0x6E, 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
    0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, 0xFC, 0x56, 0x3E, 0x4B,
    0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
    0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59,
    0x27, 0x80, 0xEC, 0x5F, 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
    0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, 0xA0, 0xE0, 0x3B, 0x4D,
    0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
    0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63,
    0x55, 0x21, 0x0C, 0x7D
}

Definition at line 73 of file rvk.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), and _rvk_emu_aes64ds().

_rvk_emu_sm4_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_sm4_sbox[256]

Initial value:

= {
    0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2,
    0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3,
    0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4,
    0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
    0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA,
    0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA,
    0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2,
    0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
    0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B,
    0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52,
    0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2,
    0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
    0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30,
    0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60,
    0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45,
    0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
    0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41,
    0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD,
    0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A,
    0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
    0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E,
    0xD7, 0xCB, 0x39, 0x48
}

Definition at line 99 of file rvk.hh.

Referenced by _rvk_emu_sm4ed(), and _rvk_emu_sm4ks().

a

Bitfield<6> gem5::RiscvISA::a

Definition at line 74 of file pagetable.hh.

Referenced by _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), f_to_i(), f_to_nf(), f_to_ni(), f_to_nui(), f_to_ui(), f_to_wf(), f_to_wi(), f_to_wui(), fadd(), fclassify(), fdiv(), feq(), fle(), flt(), fmadd(), fmax(), fmin(), fmul(), fneg(), frecip7(), frsqrte7(), fsgnj(), fsgnj16(), fsgnj32(), fsgnj64(), fsqrt(), fsub(), ftype(), ftype_freg(), fwiden(), i_to_f(), i_to_nf(), i_to_wf(), gem5::RiscvISA::PMP::pmpGetAField(), ui_to_f(), ui_to_nf(), ui_to_wf(), and gem5::RiscvISA::PCState::zcmtPc().

all

Bitfield<31, 0> gem5::RiscvISA::all

Definition at line 77 of file types.hh.

Referenced by gem5::BaseRemoteGDB::cmdIsThreadAlive(), gem5::BaseRemoteGDB::cmdSetThread(), gem5::networking::Ip6Hdr::extensionLength(), gem5::networking::Ip6Hdr::getExt(), gem5::networking::IpHdr::options(), gem5::networking::TcpHdr::options(), gem5::networking::Ip6Hdr::proto(), gem5::System::remove(), gem5::System::schedule(), gem5::ArmISA::VldSingleOp::VldSingleOp(), and gem5::ArmISA::VstSingleOp::VstSingleOp().

amofunct

Bitfield<31, 27> gem5::RiscvISA::amofunct

Definition at line 118 of file types.hh.

AMOTempReg

auto & gem5::RiscvISA::AMOTempReg = int_reg::Ureg0

Definition at line 144 of file int.hh.

aq

Bitfield<26> gem5::RiscvISA::aq

Definition at line 119 of file types.hh.

ar

Bitfield<12, 10> gem5::RiscvISA::ar

Definition at line 225 of file pra_constants.hh.

ArgumentRegs

RegId gem5::RiscvISA::ArgumentRegs[]

inlineconstexpr

Initial value:

= {
    int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
    int_reg::A4, int_reg::A5, int_reg::A6, int_reg::A7
}

Definition at line 147 of file int.hh.

Referenced by gem5::RiscvSemihosting::RiscvSemihostingAbi< ArgType >::State::State().

aseDn

Bitfield<12, 8> gem5::RiscvISA::aseDn

Definition at line 83 of file pra_constants.hh.

aseUp

gem5::RiscvISA::aseUp

Definition at line 79 of file pra_constants.hh.

asid

Bitfield< 23, 16 > gem5::RiscvISA::asid

Definition at line 47 of file pagetable.hh.

Referenced by EndBitUnion(), gem5::RiscvISA::TLB::getTableWalkerPort(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::TLB::lookup(), and gem5::RiscvISA::TLB::remove().

at

Bitfield<14, 13> gem5::RiscvISA::at

Definition at line 224 of file pra_constants.hh.

badVPN2

Bitfield<22, 4> gem5::RiscvISA::badVPN2

Definition at line 67 of file pra_constants.hh.

base

gem5::RiscvISA::base

Definition at line 1453 of file misc.hh.

Referenced by gem5::ruby::addressOffset(), gem5::FreeList< T >::allocate(), gem5::statistics::Hdf5::beginGroup(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::SMMUTranslationProcess::doReadPTE(), gem5::exclude(), gem5::exclude(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::FreeList< T >::FreeList(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::ruby::CHIGenericController::initNetQueues(), gem5::FreeList< T >::insert(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::loader::ElfObject::loadSomeSymbols(), gem5::statistics::DistPrint::operator()(), gem5::statistics::SparseHistPrint::operator()(), gem5::statistics::VectorPrint::operator()(), gem5::operator-(), gem5::operator-(), gem5::operator-=(), gem5::operator-=(), gem5::Gicv3Its::pageAddress(), gem5::RiscvISA::PMP::pmpDecodeNapot(), gem5::ItsProcess::readDeviceTable(), gem5::ItsProcess::readIrqCollectionTable(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::EtherLink::Link::serialize(), gem5::EthPacketData::serialize(), gem5::IdeController::Channel::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::Intel8254Timer::serialize(), gem5::loader::SymbolTable::serialize(), gem5::MC146818::serialize(), gem5::PacketFifo::serialize(), gem5::PacketFifoEntry::serialize(), gem5::PM4PacketProcessor::serialize(), gem5::SDMAEngine::serialize(), gem5::Time::serialize(), gem5::Shader::setLdsApe(), gem5::AMDGPUVM::setMMHUBBase(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::Shader::setScratchApe(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::WalkerState::startFunctional(), gem5::VegaISA::Walker::startTiming(), gem5::ArmISA::SyscallTable32::SyscallTable32(), gem5::ArmISA::SyscallTable64::SyscallTable64(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), gem5::MemTest::tick(), gem5::AMDGPUVM::UserTranslationGen::translate(), gem5::VegaISA::GpuTLB::translationReturn(), gem5::EtherLink::Link::unserialize(), gem5::EthPacketData::unserialize(), gem5::IdeController::Channel::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::Intel8254Timer::unserialize(), gem5::loader::SymbolTable::unserialize(), gem5::MC146818::unserialize(), gem5::MemPool::unserialize(), gem5::PacketFifo::unserialize(), gem5::PacketFifoEntry::unserialize(), gem5::PM4PacketProcessor::unserialize(), gem5::SDMAEngine::unserialize(), gem5::Time::unserialize(), gem5::MipsISA::MipsFaultBase::vect(), gem5::Packet::writeData(), gem5::ItsProcess::writeDeviceTable(), and gem5::ItsProcess::writeIrqCollectionTable().

be

Bitfield<15> gem5::RiscvISA::be

Definition at line 223 of file pra_constants.hh.

bev

Bitfield<22> gem5::RiscvISA::bev

Definition at line 117 of file pra_constants.hh.

bimm12bit11

Bitfield<7> gem5::RiscvISA::bimm12bit11

Definition at line 98 of file types.hh.

bimm12bits10to5

Bitfield<30, 25> gem5::RiscvISA::bimm12bits10to5

Definition at line 100 of file types.hh.

bimm12bits4to1

Bitfield<11, 8> gem5::RiscvISA::bimm12bits4to1

Definition at line 99 of file types.hh.

bit30

Bitfield<30> gem5::RiscvISA::bit30

Definition at line 175 of file types.hh.

bit31

Bitfield<31> gem5::RiscvISA::bit31

Definition at line 174 of file types.hh.

bit31_25

Bitfield<31, 25> gem5::RiscvISA::bit31_25

Definition at line 182 of file types.hh.

bit31_30

Bitfield<31, 30> gem5::RiscvISA::bit31_30

Definition at line 178 of file types.hh.

c

Bitfield<5, 3> gem5::RiscvISA::c

Definition at line 59 of file pra_constants.hh.

Referenced by gem5::RiscvISA::PCState::compressed(), fmadd(), gem5::RiscvISA::InterruptFault::InterruptFault(), gem5::RiscvISA::InterruptFault::InterruptFault(), gem5::RiscvISA::NonMaskableInterruptFault::NonMaskableInterruptFault(), gem5::RiscvISA::NonMaskableInterruptFault::NonMaskableInterruptFault(), and gem5::RiscvISA::RiscvFault::RiscvFault().

c2

Bitfield<6> gem5::RiscvISA::c2

Definition at line 241 of file pra_constants.hh.

ca

Bitfield<2> gem5::RiscvISA::ca

Definition at line 245 of file pra_constants.hh.

CAUSE_INTERRUPT_MASKS

const RegVal gem5::RiscvISA::CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = (1ULL << 31),
    [RV64] = (1ULL << 63),
}

Definition at line 1681 of file misc.hh.

Referenced by gem5::RiscvISA::RiscvFault::invoke().

cbcfe

Bitfield<6> gem5::RiscvISA::cbcfe

Definition at line 1446 of file misc.hh.

cbie

Bitfield<5,4> gem5::RiscvISA::cbie

Definition at line 1447 of file misc.hh.

cbze

Bitfield<7> gem5::RiscvISA::cbze

Definition at line 1445 of file misc.hh.

ce

Bitfield<29, 28> gem5::RiscvISA::ce

Definition at line 180 of file pra_constants.hh.

cfunct1

Bitfield<12> gem5::RiscvISA::cfunct1

Definition at line 123 of file types.hh.

cfunct2high

Bitfield<11, 10> gem5::RiscvISA::cfunct2high

Definition at line 124 of file types.hh.

cfunct2low

Bitfield< 6, 5> gem5::RiscvISA::cfunct2low

Definition at line 125 of file types.hh.

cimm1

Bitfield<12> gem5::RiscvISA::cimm1

Definition at line 149 of file types.hh.

cimm2

Bitfield< 6, 5> gem5::RiscvISA::cimm2

Definition at line 148 of file types.hh.

cimm3

Bitfield<12, 10> gem5::RiscvISA::cimm3

Definition at line 147 of file types.hh.

cimm5

Bitfield< 6, 2> gem5::RiscvISA::cimm5

Definition at line 146 of file types.hh.

cimm6

Bitfield<12, 7> gem5::RiscvISA::cimm6

Definition at line 145 of file types.hh.

cimm8

Bitfield<12, 5> gem5::RiscvISA::cimm8

Definition at line 144 of file types.hh.

cjumpimm

Bitfield<12, 2> gem5::RiscvISA::cjumpimm

Definition at line 135 of file types.hh.

cjumpimm10to10

Bitfield< 8, 8> gem5::RiscvISA::cjumpimm10to10

Definition at line 142 of file types.hh.

cjumpimm3to1

Bitfield< 5, 3> gem5::RiscvISA::cjumpimm3to1

Definition at line 136 of file types.hh.

cjumpimm4to4

Bitfield<11, 11> gem5::RiscvISA::cjumpimm4to4

Definition at line 137 of file types.hh.

cjumpimm5to5

Bitfield< 2, 2> gem5::RiscvISA::cjumpimm5to5

Definition at line 138 of file types.hh.

cjumpimm6to6

Bitfield< 7, 7> gem5::RiscvISA::cjumpimm6to6

Definition at line 139 of file types.hh.

cjumpimm7to7

Bitfield< 6, 6> gem5::RiscvISA::cjumpimm7to7

Definition at line 140 of file types.hh.

cjumpimm9to8

Bitfield<10, 9> gem5::RiscvISA::cjumpimm9to8

Definition at line 141 of file types.hh.

cjumpimmsign

Bitfield<12> gem5::RiscvISA::cjumpimmsign

Definition at line 143 of file types.hh.

coId

Bitfield<23, 16> gem5::RiscvISA::coId

Definition at line 205 of file pra_constants.hh.

compressed

Bitfield<61> gem5::RiscvISA::compressed

Definition at line 60 of file types.hh.

Referenced by gem5::RiscvISA::Decoder::decode(), gem5::RiscvISA::Decoder::decode(), and gem5::RiscvISA::Decoder::moreBytes().

conv_sgn

Bitfield<24, 20> gem5::RiscvISA::conv_sgn

Definition at line 115 of file types.hh.

coOp

gem5::RiscvISA::coOp

Definition at line 204 of file pra_constants.hh.

copcode

Bitfield<15, 13> gem5::RiscvISA::copcode

Definition at line 122 of file types.hh.

cpuNum

Bitfield<9, 9> gem5::RiscvISA::cpuNum

Definition at line 215 of file pra_constants.hh.

CSRData

const std::unordered_map<int, CSRMetadata> gem5::RiscvISA::CSRData

Definition at line 604 of file misc.hh.

Referenced by gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::ISA::getCSRDataMap(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), hwprobe_one_pair(), gem5::setRegNoEffectWithMask(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), and gem5::setRegWithMask().

csrimm

Bitfield<19, 15> gem5::RiscvISA::csrimm

Definition at line 108 of file types.hh.

Referenced by gem5::RiscvISA::CSROp::CSROp().

CSRMasks

const std::unordered_map<int, RegVal> gem5::RiscvISA::CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Definition at line 1694 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::getCSRMaskMap(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::setRegNoEffectWithMask(), and gem5::setRegWithMask().

CSRWriteMasks

const std::unordered_map<int, RegVal> gem5::RiscvISA::CSRWriteMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Definition at line 1816 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::getCSRWriteMaskMap(), and gem5::RiscvISA::ISA::setMiscReg().

css

Bitfield<3, 0> gem5::RiscvISA::css

Definition at line 163 of file pra_constants.hh.

cu0

Bitfield<28> gem5::RiscvISA::cu0

Definition at line 110 of file pra_constants.hh.

cu1

Bitfield<29> gem5::RiscvISA::cu1

Definition at line 109 of file pra_constants.hh.

cu2

Bitfield<30> gem5::RiscvISA::cu2

Definition at line 108 of file pra_constants.hh.

cu3

Bitfield<31> gem5::RiscvISA::cu3

Definition at line 107 of file pra_constants.hh.

d

Bitfield< 2 > gem5::RiscvISA::d

Definition at line 73 of file pagetable.hh.

da

Bitfield<9, 7> gem5::RiscvISA::da

Definition at line 240 of file pra_constants.hh.

dc

Bitfield<27> gem5::RiscvISA::dc

Definition at line 181 of file pra_constants.hh.

DELEGABLE_EXCPS

const RegVal gem5::RiscvISA::DELEGABLE_EXCPS

Initial value:

= 0
    | (1ULL << INST_ADDR_MISALIGNED)
    | (1ULL << INST_ACCESS)
    | (1ULL << INST_ILLEGAL)
    | (1ULL << BREAKPOINT)
    | (1ULL << LOAD_ADDR_MISALIGNED)
    | (1ULL << LOAD_ACCESS)
    | (1ULL << STORE_ADDR_MISALIGNED)
    | (1ULL << STORE_ACCESS)
    | (1ULL << ECALL_USER)
    | (1ULL << ECALL_SUPER)
    | (1ULL << ECALL_MACHINE)
    | (1ULL << INST_PAGE)
    | (1ULL << LOAD_PAGE)
    | (1ULL << STORE_PAGE)

Definition at line 154 of file fault_codes.hh.

DELEGABLE_EXCPS_WITH_RVH

const RegVal gem5::RiscvISA::DELEGABLE_EXCPS_WITH_RVH

Initial value:

= DELEGABLE_EXCPS
    | (1ULL << ECALL_VIRTUAL_SUPER)
    | (1ULL << INST_GUEST_PAGE)
    | (1ULL << LOAD_GUEST_PAGE)
    | (1ULL << VIRTUAL_INST)
    | (1ULL << STORE_GUEST_PAGE)

Definition at line 173 of file fault_codes.hh.

DELEGABLE_INTS_MASK

const RegVal gem5::RiscvISA::DELEGABLE_INTS_MASK

Initial value:

= SSI_MASK | STI_MASK | SEI_MASK |
                                   VSSI_MASK | VSTI_MASK | VSEI_MASK

Definition at line 1688 of file misc.hh.

dl

Bitfield<12, 10> gem5::RiscvISA::dl

Definition at line 239 of file pra_constants.hh.

ds

Bitfield<15, 13> gem5::RiscvISA::ds

Definition at line 238 of file pra_constants.hh.

dspp

Bitfield<10> gem5::RiscvISA::dspp

Definition at line 265 of file pra_constants.hh.

eb

Bitfield<25> gem5::RiscvISA::eb

Definition at line 315 of file pra_constants.hh.

ec

Bitfield<30> gem5::RiscvISA::ec

Definition at line 310 of file pra_constants.hh.

ed

Bitfield<29> gem5::RiscvISA::ed

Definition at line 311 of file pra_constants.hh.

ee

Bitfield<26> gem5::RiscvISA::ee

Definition at line 314 of file pra_constants.hh.

eicss

Bitfield<21, 18> gem5::RiscvISA::eicss

Definition at line 157 of file pra_constants.hh.

elpa

Bitfield<29> gem5::RiscvISA::elpa

Definition at line 80 of file pra_constants.hh.

enable_zcd

Bitfield<60> gem5::RiscvISA::enable_zcd

Definition at line 61 of file types.hh.

ep

Bitfield<1> gem5::RiscvISA::ep

Definition at line 246 of file pra_constants.hh.

erl

Bitfield<2> gem5::RiscvISA::erl

Definition at line 140 of file pra_constants.hh.

es

Bitfield<27> gem5::RiscvISA::es

Definition at line 313 of file pra_constants.hh.

esp

Bitfield<28> gem5::RiscvISA::esp

Definition at line 81 of file pra_constants.hh.

ess

Bitfield<15, 12> gem5::RiscvISA::ess

Definition at line 159 of file pra_constants.hh.

et

Bitfield<28> gem5::RiscvISA::et

Definition at line 312 of file pra_constants.hh.

event

Bitfield<10, 5> gem5::RiscvISA::event

Definition at line 300 of file pra_constants.hh.

excCode

Bitfield<6, 2> gem5::RiscvISA::excCode

Definition at line 199 of file pra_constants.hh.

exceptionBase

gem5::RiscvISA::exceptionBase

Definition at line 213 of file pra_constants.hh.

exl

Bitfield< 0 > gem5::RiscvISA::exl

Definition at line 141 of file pra_constants.hh.

fc1

Bitfield<11, 7> gem5::RiscvISA::fc1

Definition at line 132 of file types.hh.

fc2

Bitfield< 6, 2> gem5::RiscvISA::fc2

Definition at line 133 of file types.hh.

fd

Bitfield<11, 7> gem5::RiscvISA::fd

Definition at line 110 of file types.hh.

FFLAGS_MASK

const RegVal gem5::RiscvISA::FFLAGS_MASK = (1 << FRM_OFFSET) - 1

Definition at line 1678 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::readMiscReg(), and gem5::RiscvISA::ISA::setMiscReg().

fill

Bitfield< 61, 40 > gem5::RiscvISA::fill

Definition at line 57 of file pra_constants.hh.

Referenced by EndBitUnion().

fiom

Bitfield<0> gem5::RiscvISA::fiom

Definition at line 1449 of file misc.hh.

fp

Bitfield<0> gem5::RiscvISA::fp

Definition at line 247 of file pra_constants.hh.

fp2

Bitfield< 4, 2> gem5::RiscvISA::fp2

Definition at line 134 of file types.hh.

fr

Bitfield<26> gem5::RiscvISA::fr

Definition at line 113 of file pra_constants.hh.

FRM_MASK

const RegVal gem5::RiscvISA::FRM_MASK = 0x7

Definition at line 1679 of file misc.hh.

FRM_OFFSET

const off_t gem5::RiscvISA::FRM_OFFSET = 5

Definition at line 1474 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::backdoorReadCSRAllBits().

fs

Bitfield<14, 13> gem5::RiscvISA::fs

Definition at line 1349 of file misc.hh.

fs1

Bitfield<19, 15> gem5::RiscvISA::fs1

Definition at line 111 of file types.hh.

fs2

Bitfield<24, 20> gem5::RiscvISA::fs2

Definition at line 112 of file types.hh.

fs3

Bitfield<31, 27> gem5::RiscvISA::fs3

Definition at line 113 of file types.hh.

FS_OFFSET

const off_t gem5::RiscvISA::FS_OFFSET = 13

Definition at line 1472 of file misc.hh.

funct12

Bitfield<31, 20> gem5::RiscvISA::funct12

Definition at line 107 of file types.hh.

Referenced by gem5::RiscvISA::CSROp::CSROp().

funct2

Bitfield<26, 25> gem5::RiscvISA::funct2

Definition at line 116 of file types.hh.

funct3

Bitfield<14, 12> gem5::RiscvISA::funct3

Definition at line 79 of file types.hh.

funct7

Bitfield<31, 25> gem5::RiscvISA::funct7

Definition at line 82 of file types.hh.

g

Bitfield< 30 > gem5::RiscvISA::g

Definition at line 75 of file pagetable.hh.

Referenced by EndBitUnion().

gva

Bitfield< 6 > gem5::RiscvISA::gva

Definition at line 1336 of file misc.hh.

HS_INTERRUPTS

const RegVal gem5::RiscvISA::HS_INTERRUPTS = SGEI_MASK | VSSI_MASK | VSTI_MASK | VSEI_MASK

Definition at line 1691 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::readMiscReg().

hss

gem5::RiscvISA::hss

Definition at line 155 of file pra_constants.hh.

HSTATUS_GVA_MASK

const RegVal gem5::RiscvISA::HSTATUS_GVA_MASK = 1LL << 6

Definition at line 1531 of file misc.hh.

HSTATUS_HU_MASK

const RegVal gem5::RiscvISA::HSTATUS_HU_MASK = 1ULL << 9

Definition at line 1528 of file misc.hh.

HSTATUS_MASKS

const RegVal gem5::RiscvISA::HSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Initial value:

= {
    [RV32] = {
        [enums::M] = 0ULL,
        [enums::MU] = 0ULL,
        [enums::MSU] = 0ULL,
        [enums::MHSU] = 0ULL,
    },
    [RV64] = {
        [enums::M] = 0ULL,
        [enums::MU] = 0ULL,
        [enums::MSU] = 0ULL,
        [enums::MHSU] = HSTATUS_VSXL_MASK | HSTATUS_VTSR_MASK |
                        HSTATUS_VTW_MASK   | HSTATUS_VTVM_MASK |
                        HSTATUS_VGEIN_MASK | HSTATUS_HU_MASK |
                        HSTATUS_SPVP_MASK | HSTATUS_SPV_MASK |
                        HSTATUS_GVA_MASK | HSTATUS_VSBE_MASK,
    },
}

Definition at line 1589 of file misc.hh.

HSTATUS_SPV_MASK

const RegVal gem5::RiscvISA::HSTATUS_SPV_MASK = 1ULL << 7

Definition at line 1530 of file misc.hh.

HSTATUS_SPVP_MASK

const RegVal gem5::RiscvISA::HSTATUS_SPVP_MASK = 1ULL << 8

Definition at line 1529 of file misc.hh.

HSTATUS_VGEIN_MASK

const RegVal gem5::RiscvISA::HSTATUS_VGEIN_MASK = 63ULL << 12

Definition at line 1527 of file misc.hh.

HSTATUS_VSBE_MASK

const RegVal gem5::RiscvISA::HSTATUS_VSBE_MASK = 1ULL << 5

Definition at line 1532 of file misc.hh.

HSTATUS_VSXL_MASK

const RegVal gem5::RiscvISA::HSTATUS_VSXL_MASK = 3ULL << VSXL_OFFSET

Definition at line 1523 of file misc.hh.

HSTATUS_VTSR_MASK

const RegVal gem5::RiscvISA::HSTATUS_VTSR_MASK = 1ULL << 22

Definition at line 1524 of file misc.hh.

HSTATUS_VTVM_MASK

const RegVal gem5::RiscvISA::HSTATUS_VTVM_MASK = 1ULL << 20

Definition at line 1526 of file misc.hh.

HSTATUS_VTW_MASK

const RegVal gem5::RiscvISA::HSTATUS_VTW_MASK = 1ULL << 21

Definition at line 1525 of file misc.hh.

hu

Bitfield<9> gem5::RiscvISA::hu

Definition at line 1368 of file misc.hh.

i

Bitfield< 2 > gem5::RiscvISA::i

Definition at line 279 of file pra_constants.hh.

Referenced by _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_xperm32(), _rvk_emu_xperm64(), gem5::RiscvISA::VlFFTrimVlMicroOp::calcVl(), gem5::RiscvISA::ISA::copyRegsFrom(), cpumask_and(), cpumask_empty(), EndBitUnion(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VMaskMergeMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegIntrlvMicroInst::generateDisassembly(), get_cpu_online_mask(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), hwprobe_get_cpus(), hwprobe_get_values(), gem5::RiscvISA::Interrupts::Interrupts(), gem5::RiscvISA::PMP::pmpCheck(), gem5::RiscvISA::PMP::pmpReset(), gem5::RiscvISA::PMP::pmpUpdateRule(), gem5::RiscvISA::ISA::setMiscReg(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::RiscvISA::RiscvMacroInst::size(), gem5::RiscvISA::VlFFTrimVlMicroOp::VlFFTrimVlMicroOp(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(), gem5::RiscvISA::VMaskMergeMicroInst::VMaskMergeMicroInst(), and gem5::RiscvISA::VsSegIntrlvMicroInst::VsSegIntrlvMicroInst().

ia

Bitfield<18, 16> gem5::RiscvISA::ia

Definition at line 237 of file pra_constants.hh.

ie

Bitfield< 4 > gem5::RiscvISA::ie

Definition at line 142 of file pra_constants.hh.

il

Bitfield<21, 19> gem5::RiscvISA::il

Definition at line 236 of file pra_constants.hh.

im0

Bitfield<8> gem5::RiscvISA::im0

Definition at line 132 of file pra_constants.hh.

im1

Bitfield<9> gem5::RiscvISA::im1

Definition at line 131 of file pra_constants.hh.

im2

Bitfield<10> gem5::RiscvISA::im2

Definition at line 130 of file pra_constants.hh.

im3

Bitfield<11> gem5::RiscvISA::im3

Definition at line 129 of file pra_constants.hh.

im4

Bitfield<12> gem5::RiscvISA::im4

Definition at line 128 of file pra_constants.hh.

im5

Bitfield<13> gem5::RiscvISA::im5

Definition at line 127 of file pra_constants.hh.

im6

Bitfield<14> gem5::RiscvISA::im6

Definition at line 126 of file pra_constants.hh.

imm12

Bitfield<31, 20> gem5::RiscvISA::imm12

Definition at line 88 of file types.hh.

imm20

Bitfield<31, 12> gem5::RiscvISA::imm20

Definition at line 96 of file types.hh.

imm5

Bitfield<11, 7> gem5::RiscvISA::imm5

Definition at line 93 of file types.hh.

imm7

Bitfield<31, 25> gem5::RiscvISA::imm7

Definition at line 94 of file types.hh.

immsign

Bitfield<31> gem5::RiscvISA::immsign

Definition at line 101 of file types.hh.

impl

Bitfield< 4, 3 > gem5::RiscvISA::impl

Definition at line 93 of file pra_constants.hh.

index

Bitfield< 22, 0 > gem5::RiscvISA::index

Definition at line 47 of file pra_constants.hh.

Referenced by gem5::RiscvISA::Interrupts::clear(), elem_mask(), elem_mask_vseg(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::PMP::pmpUpdateAddr(), gem5::RiscvISA::Interrupts::post(), and gem5::RiscvISA::VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst().

ip0

Bitfield<8> gem5::RiscvISA::ip0

Definition at line 196 of file pra_constants.hh.

ip1

Bitfield<9> gem5::RiscvISA::ip1

Definition at line 195 of file pra_constants.hh.

ip2

Bitfield<10> gem5::RiscvISA::ip2

Definition at line 194 of file pra_constants.hh.

ip3

Bitfield<11> gem5::RiscvISA::ip3

Definition at line 193 of file pra_constants.hh.

ip4

Bitfield<12> gem5::RiscvISA::ip4

Definition at line 192 of file pra_constants.hh.

ip5

Bitfield<13> gem5::RiscvISA::ip5

Definition at line 191 of file pra_constants.hh.

ip6

Bitfield<14> gem5::RiscvISA::ip6

Definition at line 190 of file pra_constants.hh.

ipl

Bitfield<15, 10> gem5::RiscvISA::ipl

Definition at line 123 of file pra_constants.hh.

ippci

Bitfield<28, 26> gem5::RiscvISA::ippci

Definition at line 147 of file pra_constants.hh.

ipti

gem5::RiscvISA::ipti

Definition at line 146 of file pra_constants.hh.

is

Bitfield<24, 22> gem5::RiscvISA::is

Definition at line 235 of file pra_constants.hh.

ISA_EXT_C_MASK

const RegVal gem5::RiscvISA::ISA_EXT_C_MASK = 1UL << ('c' - 'a')

Definition at line 1481 of file misc.hh.

ISA_EXT_MASK

const RegVal gem5::RiscvISA::ISA_EXT_MASK = mask(26)

Definition at line 1480 of file misc.hh.

ISA_MXL_MASKS

const RegVal gem5::RiscvISA::ISA_MXL_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 3ULL << MXL_OFFSETS[RV32],
    [RV64] = 3ULL << MXL_OFFSETS[RV64],
}

Definition at line 1476 of file misc.hh.

iv

Bitfield<23> gem5::RiscvISA::iv

Definition at line 184 of file pra_constants.hh.

jt_index

Bitfield< 9, 2> gem5::RiscvISA::jt_index

Definition at line 152 of file types.hh.

k

Bitfield<1> gem5::RiscvISA::k

Definition at line 304 of file pra_constants.hh.

k0

Bitfield<2, 0> gem5::RiscvISA::k0

Definition at line 229 of file pra_constants.hh.

k23

Bitfield<30, 28> gem5::RiscvISA::k23

Definition at line 220 of file pra_constants.hh.

ksu

Bitfield<4, 3> gem5::RiscvISA::ksu

Definition at line 137 of file pra_constants.hh.

ku

Bitfield<27, 25> gem5::RiscvISA::ku

Definition at line 221 of file pra_constants.hh.

l

Bitfield<5> gem5::RiscvISA::l

Definition at line 323 of file pra_constants.hh.

local

gem5::RiscvISA::local

Definition at line 1425 of file misc.hh.

Referenced by gem5::openatFunc().

LOCAL_MASK

const RegVal gem5::RiscvISA::LOCAL_MASK = mask(63,16)

Definition at line 1631 of file misc.hh.

lpa

Bitfield<7> gem5::RiscvISA::lpa

Definition at line 267 of file pra_constants.hh.

lumop

Bitfield<24, 20> gem5::RiscvISA::lumop

Definition at line 164 of file types.hh.

m5func

Bitfield<31, 25> gem5::RiscvISA::m5func

Definition at line 154 of file types.hh.

mask

Bitfield< 11, 3 > gem5::RiscvISA::mask

Definition at line 73 of file pra_constants.hh.

Referenced by _rvk_emu_xperm32(), _rvk_emu_xperm64(), boxF16(), boxF32(), gem5::RiscvISA::PMAChecker::checkPAddrAlignment(), gem5::RiscvISA::Walker::WalkerState::checkPTEPermissions(), gem5::RiscvISA::PMAChecker::checkVAddrAlignment(), gem5::RiscvISA::TLB::doTranslate(), EndBitUnion(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), fneg(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::RiscvISA::Interrupts::globalMask(), gem5::RiscvISA::Walker::WalkerState::guestToHostPage(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::ISA::readCSR(), gem5::RiscvISA::ISA::setMiscReg(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalkGStage(), unboxF16(), unboxF32(), gem5::RiscvISA::Walker::WalkerState::walkGStage(), gem5::RiscvISA::Walker::WalkerState::walkOneStage(), gem5::RiscvISA::Walker::WalkerState::walkTwoStage(), and gem5::RiscvISA::ISA::writeCSR().

maskx

Bitfield<12, 11> gem5::RiscvISA::maskx

Definition at line 74 of file pra_constants.hh.

MaxVecLenInBytes

unsigned gem5::RiscvISA::MaxVecLenInBytes = MaxVecLenInBits >> 3

constexpr

Definition at line 187 of file types.hh.

mbe

Bitfield<37> gem5::RiscvISA::mbe

Definition at line 1337 of file misc.hh.

MBE_OFFSET

const off_t gem5::RiscvISA::MBE_OFFSET[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 5,
    [RV64] = 37,
}

Definition at line 1461 of file misc.hh.

md

Bitfield<5> gem5::RiscvISA::md

Definition at line 242 of file pra_constants.hh.

mei

Bitfield<11> gem5::RiscvISA::mei

Definition at line 1427 of file misc.hh.

MEI_MASK

const RegVal gem5::RiscvISA::MEI_MASK = 1ULL << 11

Definition at line 1633 of file misc.hh.

mew

Bitfield<28> gem5::RiscvISA::mew

Definition at line 161 of file types.hh.

MI_MASK

const RegVal gem5::RiscvISA::MI_MASK[enums::Num_PrivilegeModeSet]

Initial value:

= {
    [enums::M] = LOCAL_MASK |
                 MEI_MASK| MTI_MASK | MSI_MASK,
    [enums::MU] = LOCAL_MASK |
                  MEI_MASK| MTI_MASK | MSI_MASK,
    [enums::MSU] = LOCAL_MASK |
                   MEI_MASK | SEI_MASK |
                   MTI_MASK | STI_MASK |
                   MSI_MASK | SSI_MASK,
    [enums::MHSU] = LOCAL_MASK |
                    MEI_MASK | VSEI_MASK | SEI_MASK |
                    MTI_MASK | VSTI_MASK | STI_MASK |
                    MSI_MASK | VSSI_MASK | SSI_MASK | SGEI_MASK,
}

Definition at line 1643 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

MIDELEG_MASK

const RegVal gem5::RiscvISA::MIDELEG_MASK[enums::Num_PrivilegeModeSet]

Initial value:

= {
    [enums::M] = LOCAL_MASK,
    [enums::MU] = LOCAL_MASK,
    [enums::MSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
    [enums::MHSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
}

Definition at line 1664 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

mie

Bitfield<3> gem5::RiscvISA::mie

Definition at line 1356 of file misc.hh.

MISA_MASKS

const RegVal gem5::RiscvISA::MISA_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = ISA_MXL_MASKS[RV32] | ISA_EXT_MASK,
    [RV64] = ISA_MXL_MASKS[RV64] | ISA_EXT_MASK,
}

Definition at line 1482 of file misc.hh.

MiscRegNames

const std::array<const char *, NUM_MISCREGS> gem5::RiscvISA::MiscRegNames

Definition at line 72 of file isa.cc.

Referenced by gem5::RiscvISA::ISA::hpmCounterCheck(), gem5::RiscvISA::ISA::readMiscRegNoEffect(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::RiscvISA::ISA::setMiscRegNoEffect().

mmuSize

Bitfield<30, 25> gem5::RiscvISA::mmuSize

Definition at line 234 of file pra_constants.hh.

mnpp

gem5::RiscvISA::mnpp

Definition at line 1382 of file misc.hh.

mnv

Bitfield<7> gem5::RiscvISA::mnv

Definition at line 1383 of file misc.hh.

mode

Bitfield< 5, 0 > gem5::RiscvISA::mode

Definition at line 46 of file pagetable.hh.

Referenced by gem5::RiscvISA::BasePMAChecker::check(), gem5::RiscvISA::PMAChecker::check(), gem5::RiscvISA::PMAChecker::checkPAddrAlignment(), gem5::RiscvISA::TLB::checkPermissions(), gem5::RiscvISA::BasePMAChecker::checkVAddrAlignment(), gem5::RiscvISA::PMAChecker::checkVAddrAlignment(), gem5::RiscvISA::PMP::createAddrfault(), gem5::RiscvISA::PMAChecker::createMisalignFault(), gem5::RiscvISA::TLB::createPagefault(), gem5::RiscvISA::TLB::demapPage(), gem5::RiscvISA::TLB::doTranslate(), EndBitUnion(), gem5::RiscvISA::TLB::evictLRU(), f_to_i(), f_to_ni(), f_to_nui(), f_to_ui(), f_to_wi(), f_to_wui(), gem5::RiscvISA::TLB::finalizePhysical(), gem5::RiscvISA::MMU::getMemAccessInfo(), gem5::RiscvISA::TLB::getMemAccessInfo(), gem5::RiscvISA::TLB::getTableWalkerPort(), gem5::RiscvISA::MMU::getValidAddr(), gem5::RiscvISA::TLB::getValidAddr(), getVPNFromVAddr(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::TLB::lookup(), gem5::RiscvISA::PMP::pmpCheck(), gem5::RiscvISA::TLB::translate(), gem5::RiscvISA::TLB::translateAtomic(), gem5::RiscvISA::MMU::translateFunctional(), gem5::RiscvISA::TLB::translateFunctional(), and gem5::RiscvISA::TLB::translateTiming().

mop

Bitfield<27, 26> gem5::RiscvISA::mop

Definition at line 162 of file types.hh.

mpie

Bitfield<7> gem5::RiscvISA::mpie

Definition at line 1353 of file misc.hh.

mpp

Bitfield<12, 11> gem5::RiscvISA::mpp

Definition at line 1350 of file misc.hh.

mprv

Bitfield<17> gem5::RiscvISA::mprv

Definition at line 1347 of file misc.hh.

mpv

Bitfield<39> gem5::RiscvISA::mpv

Definition at line 1335 of file misc.hh.

msi

Bitfield<3> gem5::RiscvISA::msi

Definition at line 1433 of file misc.hh.

MSI_MASK

const RegVal gem5::RiscvISA::MSI_MASK = 1ULL << 3

Definition at line 1639 of file misc.hh.

MSTATUS_MASKS

const RegVal gem5::RiscvISA::MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Definition at line 1535 of file misc.hh.

MSTATUSH_MASKS

const RegVal gem5::RiscvISA::MSTATUSH_MASKS[enums::Num_PrivilegeModeSet]

Initial value:

= {
    [enums::M] = STATUS_MBE_MASK[RV32],
    [enums::MU] = STATUS_MBE_MASK[RV32],
    [enums::MSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32],
}

Definition at line 1582 of file misc.hh.

mt

Bitfield< 2 > gem5::RiscvISA::mt

Definition at line 226 of file pra_constants.hh.

mti

Bitfield<7> gem5::RiscvISA::mti

Definition at line 1430 of file misc.hh.

MTI_MASK

const RegVal gem5::RiscvISA::MTI_MASK = 1ULL << 7

Definition at line 1636 of file misc.hh.

mx

Bitfield<24> gem5::RiscvISA::mx

Definition at line 115 of file pra_constants.hh.

mxr

Bitfield<19> gem5::RiscvISA::mxr

Definition at line 1345 of file misc.hh.

Referenced by gem5::RiscvISA::TLB::checkPermissions().

NapotShift

const Addr gem5::RiscvISA::NapotShift = 4

Definition at line 55 of file page_size.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::checkPTEPermissions(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), and gem5::RiscvISA::Walker::WalkerState::stepWalkGStage().

nf

Bitfield<31, 29> gem5::RiscvISA::nf

Definition at line 160 of file types.hh.

nmi

Bitfield<19> gem5::RiscvISA::nmi

Definition at line 120 of file pra_constants.hh.

nmie

Bitfield<3> gem5::RiscvISA::nmie

Definition at line 1384 of file misc.hh.

NumVecInternalRegs

const int gem5::RiscvISA::NumVecInternalRegs = 8

Definition at line 55 of file vector.hh.

NumVecRegs

const int gem5::RiscvISA::NumVecRegs = NumVecStandardRegs + NumVecInternalRegs

Definition at line 56 of file vector.hh.

Referenced by registerName().

NumVecStandardRegs

const int gem5::RiscvISA::NumVecStandardRegs = 32

Definition at line 54 of file vector.hh.

opcode

Bitfield< 6, 0> gem5::RiscvISA::opcode

Definition at line 75 of file types.hh.

opcode5

Bitfield< 6, 2> gem5::RiscvISA::opcode5

Definition at line 74 of file types.hh.

p

Bitfield<0> gem5::RiscvISA::p

Definition at line 326 of file pra_constants.hh.

Referenced by gem5::RiscvISA::BareMetal::BareMetal(), BitUnion32(), gem5::RiscvISA::BootloaderKernelWorkload::BootloaderKernelWorkload(), gem5::RiscvISA::Decoder::decodeInst(), gem5::RiscvISA::Decoder::Decoder(), gem5::RiscvISA::EmuLinux::EmuLinux(), gem5::RiscvISA::FsLinux::FsLinux(), gem5::RiscvISA::Interrupts::Interrupts(), gem5::RiscvISA::ISA::ISA(), gem5::RiscvISA::MMU::MMU(), gem5::RiscvISA::BareMetal::PARAMS(), gem5::RiscvISA::SEWorkload::SEWorkload(), gem5::RiscvISA::TLB::TLB(), and gem5::RiscvISA::TLB::translate().

PageBytes

const Addr gem5::RiscvISA::PageBytes = 1ULL << PageShift

Definition at line 54 of file page_size.hh.

Referenced by gem5::RiscvSemihosting::isSemihostingEBreak(), and gem5::RiscvISA::MMU::translateFunctional().

PageShift

const Addr gem5::RiscvISA::PageShift = 12

Definition at line 53 of file page_size.hh.

Referenced by gem5::RiscvISA::TLB::doTranslate(), gem5::RiscvISA::EmuLinux::EmuLinux(), gem5::RiscvISA::Walker::WalkerState::guestToHostPage(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::TLB::insert(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::startFunctional(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalkGStage(), and gem5::RiscvISA::Walker::WalkerState::walkGStage().

pc

Bitfield<4> gem5::RiscvISA::pc

Definition at line 243 of file pra_constants.hh.

Referenced by gem5::RiscvISA::RiscvMicroInst::advancePC(), gem5::RiscvISA::RiscvStaticInst::advancePC(), gem5::RiscvISA::RiscvStaticInst::advancePC(), gem5::RiscvISA::PCState::branching(), gem5::RiscvISA::BreakpointFault::BreakpointFault(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly(), gem5::RiscvISA::BSOp::generateDisassembly(), gem5::RiscvISA::CompRegOp::generateDisassembly(), gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::Load::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::LoadReservedMicro::generateDisassembly(), gem5::RiscvISA::MemFenceMicro::generateDisassembly(), gem5::RiscvISA::PseudoOp::generateDisassembly(), gem5::RiscvISA::RegOp::generateDisassembly(), gem5::RiscvISA::Store::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::StoreCondMicro::generateDisassembly(), gem5::RiscvISA::SystemOp::generateDisassembly(), gem5::RiscvISA::Unknown::generateDisassembly(), gem5::RiscvISA::VConfOp::generateDisassembly(), gem5::RiscvISA::VCpyVsMicroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMacroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMicroInst::generateDisassembly(), gem5::RiscvISA::VectorNonSplitInst::generateDisassembly(), gem5::RiscvISA::VectorNopMicroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMacroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMicroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MacroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MicroInst::generateDisassembly(), gem5::RiscvISA::VlElementMacroInst::generateDisassembly(), gem5::RiscvISA::VlElementMicroInst::generateDisassembly(), gem5::RiscvISA::VleMacroInst::generateDisassembly(), gem5::RiscvISA::VleMicroInst::generateDisassembly(), gem5::RiscvISA::VlFFTrimVlMicroOp::generateDisassembly(), gem5::RiscvISA::VlIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegMacroInst::generateDisassembly(), gem5::RiscvISA::VlSegMicroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VMaskMergeMicroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VPinVdMicroInst::generateDisassembly(), gem5::RiscvISA::VsElementMacroInst::generateDisassembly(), gem5::RiscvISA::VsElementMicroInst::generateDisassembly(), gem5::RiscvISA::VseMacroInst::generateDisassembly(), gem5::RiscvISA::VseMicroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegMacroInst::generateDisassembly(), gem5::RiscvISA::VsSegMicroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VxsatMicroInst::generateDisassembly(), gem5::RiscvISA::ZcmtSecondFetchInst::generateDisassembly(), and gem5::RiscvISA::Decoder::moreBytes().

pci

Bitfield<26> gem5::RiscvISA::pci

Definition at line 182 of file pra_constants.hh.

perm

Bitfield<3, 1> gem5::RiscvISA::perm

Definition at line 77 of file pagetable.hh.

Referenced by gem5::ruby::CacheMemory::recordCacheContents().

pfn

Bitfield<29, 6> gem5::RiscvISA::pfn

Definition at line 58 of file pra_constants.hh.

pmm

Bitfield<33,32> gem5::RiscvISA::pmm

Definition at line 1443 of file misc.hh.

ppn

Bitfield< 53, 10 > gem5::RiscvISA::ppn

Definition at line 48 of file pagetable.hh.

Referenced by gem5::prefetch::SignaturePath::addPrefetch(), gem5::prefetch::SignaturePath::auxiliaryPrefetcher(), gem5::prefetch::SignaturePathV2::auxiliaryPrefetcher(), gem5::prefetch::SignaturePath::calculatePrefetch(), gem5::prefetch::SignaturePath::getSignatureEntry(), and gem5::RiscvISA::Walker::WalkerState::walkGStage().

ppn0

Bitfield<18, 10> gem5::RiscvISA::ppn0

Definition at line 72 of file pagetable.hh.

ppn1

Bitfield<27, 19> gem5::RiscvISA::ppn1

Definition at line 71 of file pagetable.hh.

ppn2

Bitfield<53, 28> gem5::RiscvISA::ppn2

Definition at line 70 of file pagetable.hh.

pred

Bitfield<27, 24> gem5::RiscvISA::pred

Definition at line 91 of file types.hh.

Referenced by gem5::branch_prediction::TAGEBase::baseUpdate(), gem5::branch_prediction::TAGEBase::condBranchUpdate(), gem5::MSHR::promoteIf(), gem5::MSHR::promoteReadable(), gem5::MSHR::promoteWritable(), and gem5::branch_prediction::MultiperspectivePerceptron::train().

procId

Bitfield<15, 8> gem5::RiscvISA::procId

Definition at line 206 of file pra_constants.hh.

pss

Bitfield<9, 6> gem5::RiscvISA::pss

Definition at line 161 of file pra_constants.hh.

pState

Bitfield<7, 6> gem5::RiscvISA::pState

Definition at line 322 of file pra_constants.hh.

pTagLo

gem5::RiscvISA::pTagLo

Definition at line 321 of file pra_constants.hh.

pteBase

gem5::RiscvISA::pteBase

Definition at line 66 of file pra_constants.hh.

PushPopRegList

const std::vector<RegId> gem5::RiscvISA::PushPopRegList

Initial value:

= {
    int_reg::S11, int_reg::S10, int_reg::S9, int_reg::S8,
    int_reg::S7, int_reg::S6, int_reg::S5, int_reg::S4,
    int_reg::S3, int_reg::S2, int_reg::S1, int_reg::S0,
    int_reg::Ra
}

Definition at line 152 of file int.hh.

Referenced by gem5::RiscvISA::CmMacroInst::getRlistStr().

px

Bitfield<23> gem5::RiscvISA::px

Definition at line 116 of file pra_constants.hh.

quadRant

Bitfield< 1, 0> gem5::RiscvISA::quadRant

Definition at line 73 of file types.hh.

r

Bitfield< 1 > gem5::RiscvISA::r

Definition at line 80 of file pagetable.hh.

Referenced by _rvk_emu_xperm32(), _rvk_emu_xperm64(), EndBitUnion(), EndBitUnion(), f16(), f32(), f64(), gem5::RiscvISA::IllegalFrmFault::IllegalFrmFault(), and gem5::RiscvISA::IllegalInstFault::IllegalInstFault().

r0

Bitfield<3> gem5::RiscvISA::r0

Definition at line 139 of file pra_constants.hh.

r1s

Bitfield< 9, 7> gem5::RiscvISA::r1s

Definition at line 130 of file types.hh.

r2s

Bitfield< 4, 2> gem5::RiscvISA::r2s

Definition at line 131 of file types.hh.

random

gem5::RiscvISA::random

Definition at line 53 of file pra_constants.hh.

rc1

Bitfield<11, 7> gem5::RiscvISA::rc1

Definition at line 126 of file types.hh.

rc2

Bitfield< 6, 2> gem5::RiscvISA::rc2

Definition at line 127 of file types.hh.

rd

Bitfield<11, 7> gem5::RiscvISA::rd

Definition at line 78 of file types.hh.

re

Bitfield<25> gem5::RiscvISA::re

Definition at line 114 of file pra_constants.hh.

reserved

Bitfield<62, 54> gem5::RiscvISA::reserved

Definition at line 68 of file pagetable.hh.

Referenced by gem5::igbreg::Regs::FWSM::ADD_FIELD32(), gem5::igbreg::Regs::SWSM::ADD_FIELD32(), gem5::PoolManager::allocateRegion(), gem5::EndBitUnion(), gem5::qemu::FwCfg::Directory::update(), gem5::X86ISA::intelmp::BusHierarchy::writeOut(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), and gem5::X86ISA::intelmp::Processor::writeOut().

ReturnAddrReg

auto& gem5::RiscvISA::ReturnAddrReg = int_reg::Ra

inlineconstexpr

Definition at line 140 of file int.hh.

Referenced by gem5::RiscvISA::CmMacroInst::getRlistStr().

ReturnValueReg

auto & gem5::RiscvISA::ReturnValueReg = int_reg::A0

Definition at line 143 of file int.hh.

Referenced by gem5::guest_abi::Result< Abi, RiscvSemihosting::RetErrno >::store(), gem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI32, SyscallReturn >::store(), and gem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI64, SyscallReturn >::store().

rev

Bitfield<7, 0> gem5::RiscvISA::rev

Definition at line 207 of file pra_constants.hh.

ripl

Bitfield<15, 10> gem5::RiscvISA::ripl

Definition at line 187 of file pra_constants.hh.

rl

Bitfield<25> gem5::RiscvISA::rl

Definition at line 120 of file types.hh.

rlist

Bitfield< 7, 4> gem5::RiscvISA::rlist

Definition at line 150 of file types.hh.

round_mode

Bitfield<14, 12> gem5::RiscvISA::round_mode

Definition at line 114 of file types.hh.

rp1

Bitfield< 9, 7> gem5::RiscvISA::rp1

Definition at line 128 of file types.hh.

rp2

Bitfield< 4, 2> gem5::RiscvISA::rp2

Definition at line 129 of file types.hh.

rs1

Bitfield<19, 15> gem5::RiscvISA::rs1

Definition at line 80 of file types.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64ds(), _rvk_emu_aes64dsm(), _rvk_emu_aes64es(), _rvk_emu_aes64esm(), _rvk_emu_aes64im(), _rvk_emu_aes64ks1i(), _rvk_emu_aes64ks2(), _rvk_emu_brev8_32(), _rvk_emu_brev8_64(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_rol_32(), _rvk_emu_rol_64(), _rvk_emu_ror_32(), _rvk_emu_ror_64(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), _rvk_emu_sha256sum1(), _rvk_emu_sha512sig0(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0(), _rvk_emu_sha512sum0r(), _rvk_emu_sha512sum1(), _rvk_emu_sha512sum1r(), _rvk_emu_shfl_32(), _rvk_emu_sll_32(), _rvk_emu_sll_64(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_srl_32(), _rvk_emu_srl_64(), _rvk_emu_unshfl_32(), _rvk_emu_unzip_32(), _rvk_emu_xperm32(), _rvk_emu_xperm4_32(), _rvk_emu_xperm4_64(), _rvk_emu_xperm64(), _rvk_emu_xperm8_32(), _rvk_emu_xperm8_64(), _rvk_emu_zip_32(), div(), divu(), mulh(), mulhsu(), mulhu(), rem(), and remu().

rs2

Bitfield<24, 20> gem5::RiscvISA::rs2

Definition at line 81 of file types.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64ds(), _rvk_emu_aes64dsm(), _rvk_emu_aes64es(), _rvk_emu_aes64esm(), _rvk_emu_aes64ks2(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_rol_32(), _rvk_emu_rol_64(), _rvk_emu_ror_32(), _rvk_emu_ror_64(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), _rvk_emu_sha512sum1r(), _rvk_emu_shfl_32(), _rvk_emu_sll_32(), _rvk_emu_sll_64(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_srl_32(), _rvk_emu_srl_64(), _rvk_emu_unshfl_32(), _rvk_emu_xperm32(), _rvk_emu_xperm4_32(), _rvk_emu_xperm4_64(), _rvk_emu_xperm64(), _rvk_emu_xperm8_32(), _rvk_emu_xperm8_64(), div(), divu(), mulh(), mulhsu(), mulhu(), rem(), and remu().

RV32

enums::RiscvType gem5::RiscvISA::RV32 = enums::RV32

constexpr

Definition at line 56 of file pcstate.hh.

Referenced by gem5::RiscvISA::ISA::clear(), EndBitUnion(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::TLB::getValidAddr(), gem5::RiscvProcess32::initState(), gem5::RiscvISA::Decoder::moreBytes(), gem5::Clint::raiseInterruptPin(), gem5::RiscvISA::ISA::readMiscReg(), gem5::RiscvISA::RiscvStaticInst::rvSelect(), gem5::RiscvISA::ISA::rvSext(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs().

rv32_mxl

Bitfield<31, 30> gem5::RiscvISA::rv32_mxl

Definition at line 1394 of file misc.hh.

rv32_sd

Bitfield<31> gem5::RiscvISA::rv32_sd

Definition at line 1341 of file misc.hh.

RV64

enums::RiscvType gem5::RiscvISA::RV64 = enums::RV64

constexpr

Definition at line 57 of file pcstate.hh.

Referenced by gem5::RiscvISA::ISA::clear(), EndBitUnion(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::RiscvProcess64::initState(), gem5::RiscvISA::RemoteGDB::insertHardBreak(), gem5::RiscvISA::ISA::readMiscReg(), gem5::RiscvISA::RemoteGDB::removeHardBreak(), gem5::RiscvISA::ISA::setMiscReg(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), and gem5::RiscvISA::CmMacroInst::stackAdj().

rv64_mxl

gem5::RiscvISA::rv64_mxl

Definition at line 1393 of file misc.hh.

rv_type

gem5::RiscvISA::rv_type

Definition at line 59 of file types.hh.

rva

Bitfield<0> gem5::RiscvISA::rva

Definition at line 1415 of file misc.hh.

rvb

Bitfield<1> gem5::RiscvISA::rvb

Definition at line 1414 of file misc.hh.

rvc

Bitfield<2> gem5::RiscvISA::rvc

Definition at line 1413 of file misc.hh.

rvd

Bitfield<3> gem5::RiscvISA::rvd

Definition at line 1412 of file misc.hh.

rve

Bitfield<4> gem5::RiscvISA::rve

Definition at line 1411 of file misc.hh.

rvf

Bitfield<5> gem5::RiscvISA::rvf

Definition at line 1410 of file misc.hh.

rvg

Bitfield<6> gem5::RiscvISA::rvg

Definition at line 1409 of file misc.hh.

rvh

Bitfield<7> gem5::RiscvISA::rvh

Definition at line 1408 of file misc.hh.

rvi

Bitfield<8> gem5::RiscvISA::rvi

Definition at line 1407 of file misc.hh.

rvj

Bitfield<9> gem5::RiscvISA::rvj

Definition at line 1406 of file misc.hh.

rvk

Bitfield<10> gem5::RiscvISA::rvk

Definition at line 1405 of file misc.hh.

rvl

Bitfield<11> gem5::RiscvISA::rvl

Definition at line 1404 of file misc.hh.

rvm

Bitfield<12> gem5::RiscvISA::rvm

Definition at line 1403 of file misc.hh.

rvn

Bitfield<13> gem5::RiscvISA::rvn

Definition at line 1402 of file misc.hh.

rvp

Bitfield<15> gem5::RiscvISA::rvp

Definition at line 1401 of file misc.hh.

rvq

Bitfield<16> gem5::RiscvISA::rvq

Definition at line 1400 of file misc.hh.

rvs

Bitfield<18> gem5::RiscvISA::rvs

Definition at line 1399 of file misc.hh.

rvt

Bitfield<19> gem5::RiscvISA::rvt

Definition at line 1398 of file misc.hh.

rvu

Bitfield<20> gem5::RiscvISA::rvu

Definition at line 1397 of file misc.hh.

rvv

Bitfield<21> gem5::RiscvISA::rvv

Definition at line 1396 of file misc.hh.

rvx

Bitfield<23> gem5::RiscvISA::rvx

Definition at line 1395 of file misc.hh.

s

Bitfield<2> gem5::RiscvISA::s

Definition at line 303 of file pra_constants.hh.

Referenced by gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::RiscvISA::VsSegIntrlvMicroInst::execute(), gem5::RiscvISA::VConfOp::generateZimmDisassembly(), and gem5::RiscvISA::CmMacroInst::getRlistStr().

sa

Bitfield<3, 0> gem5::RiscvISA::sa

Definition at line 259 of file pra_constants.hh.

sbe

Bitfield<36> gem5::RiscvISA::sbe

Definition at line 1338 of file misc.hh.

SBE_OFFSET

const off_t gem5::RiscvISA::SBE_OFFSET[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 4,
    [RV64] = 36,
}

Definition at line 1465 of file misc.hh.

sei

Bitfield<9> gem5::RiscvISA::sei

Definition at line 1429 of file misc.hh.

SEI_MASK

const RegVal gem5::RiscvISA::SEI_MASK = 1ULL << 9

Definition at line 1635 of file misc.hh.

sgei

Bitfield<12> gem5::RiscvISA::sgei

Definition at line 1426 of file misc.hh.

SGEI_MASK

const RegVal gem5::RiscvISA::SGEI_MASK = 1ULL << 12

Definition at line 1632 of file misc.hh.

shamt5

Bitfield<24, 20> gem5::RiscvISA::shamt5

Definition at line 85 of file types.hh.

shamt6

Bitfield<25, 20> gem5::RiscvISA::shamt6

Definition at line 86 of file types.hh.

SI_MASK

const RegVal gem5::RiscvISA::SI_MASK[enums::Num_PrivilegeModeSet]

Initial value:

= {
    [enums::M] = LOCAL_MASK,
    [enums::MU] = LOCAL_MASK,
    [enums::MSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
    [enums::MHSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
}

Definition at line 1658 of file misc.hh.

sie

Bitfield<1> gem5::RiscvISA::sie

Definition at line 1357 of file misc.hh.

simm3

Bitfield<17, 15> gem5::RiscvISA::simm3

Definition at line 172 of file types.hh.

sl

Bitfield<7, 4> gem5::RiscvISA::sl

Definition at line 258 of file pra_constants.hh.

sm

Bitfield<1> gem5::RiscvISA::sm

Definition at line 273 of file pra_constants.hh.

sp

Bitfield<4> gem5::RiscvISA::sp

Definition at line 270 of file pra_constants.hh.

spie

Bitfield<5> gem5::RiscvISA::spie

Definition at line 1355 of file misc.hh.

spimm

Bitfield< 3, 2> gem5::RiscvISA::spimm

Definition at line 151 of file types.hh.

spp

Bitfield<8> gem5::RiscvISA::spp

Definition at line 1352 of file misc.hh.

spv

Bitfield<7> gem5::RiscvISA::spv

Definition at line 1370 of file misc.hh.

spvp

Bitfield<8> gem5::RiscvISA::spvp

Definition at line 1369 of file misc.hh.

sr

Bitfield<20> gem5::RiscvISA::sr

Definition at line 119 of file pra_constants.hh.

srType

Bitfield<30> gem5::RiscvISA::srType

Definition at line 84 of file types.hh.

ss

Bitfield<11, 8> gem5::RiscvISA::ss

Definition at line 257 of file pra_constants.hh.

Referenced by gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly(), gem5::RiscvISA::BSOp::generateDisassembly(), gem5::RiscvISA::CompRegOp::generateDisassembly(), gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::Load::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::LoadReservedMicro::generateDisassembly(), gem5::RiscvISA::MemFenceMicro::generateDisassembly(), gem5::RiscvISA::RegOp::generateDisassembly(), gem5::RiscvISA::Store::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::StoreCondMicro::generateDisassembly(), gem5::RiscvISA::SystemOp::generateDisassembly(), gem5::RiscvISA::VConfOp::generateDisassembly(), gem5::RiscvISA::VCpyVsMicroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMacroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMicroInst::generateDisassembly(), gem5::RiscvISA::VectorNonSplitInst::generateDisassembly(), gem5::RiscvISA::VectorNopMicroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMacroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMicroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MacroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MicroInst::generateDisassembly(), gem5::RiscvISA::VlElementMacroInst::generateDisassembly(), gem5::RiscvISA::VlElementMicroInst::generateDisassembly(), gem5::RiscvISA::VleMacroInst::generateDisassembly(), gem5::RiscvISA::VleMicroInst::generateDisassembly(), gem5::RiscvISA::VlFFTrimVlMicroOp::generateDisassembly(), gem5::RiscvISA::VlIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegMacroInst::generateDisassembly(), gem5::RiscvISA::VlSegMicroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VlWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VMaskMergeMicroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VMvWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VPinVdMicroInst::generateDisassembly(), gem5::RiscvISA::VsElementMacroInst::generateDisassembly(), gem5::RiscvISA::VsElementMicroInst::generateDisassembly(), gem5::RiscvISA::VseMacroInst::generateDisassembly(), gem5::RiscvISA::VseMicroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegIntrlvMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegMacroInst::generateDisassembly(), gem5::RiscvISA::VsSegMicroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMacroInst::generateDisassembly(), gem5::RiscvISA::VsWholeMicroInst::generateDisassembly(), gem5::RiscvISA::VxsatMicroInst::generateDisassembly(), and gem5::RiscvISA::ZcmtSecondFetchInst::generateDisassembly().

ssi

Bitfield<1> gem5::RiscvISA::ssi

Definition at line 1435 of file misc.hh.

SSI_MASK

const RegVal gem5::RiscvISA::SSI_MASK = 1ULL << 1

Definition at line 1641 of file misc.hh.

SSTATUS_MASKS

const RegVal gem5::RiscvISA::SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Initial value:

= {
    [RV32] = {
        [enums::M] = 0ULL,
        [enums::MU] = 0ULL,
        [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK |
                       STATUS_SUM_MASK |
                       STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
                       STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
    },
    [RV64] = {
        [enums::M] = 0ULL,
        [enums::MU] = 0ULL,
        [enums::MSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
                       STATUS_MXR_MASK | STATUS_SUM_MASK |
                       STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
                       STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
        [enums::MHSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
                        STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_UBE_MASK |
                        STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
                        STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
    },
}

Definition at line 1608 of file misc.hh.

ssv0

Bitfield<3, 0> gem5::RiscvISA::ssv0

Definition at line 174 of file pra_constants.hh.

ssv1

Bitfield<7, 4> gem5::RiscvISA::ssv1

Definition at line 173 of file pra_constants.hh.

ssv2

Bitfield<11, 8> gem5::RiscvISA::ssv2

Definition at line 172 of file pra_constants.hh.

ssv3

Bitfield<15, 12> gem5::RiscvISA::ssv3

Definition at line 171 of file pra_constants.hh.

ssv4

Bitfield<19, 16> gem5::RiscvISA::ssv4

Definition at line 170 of file pra_constants.hh.

ssv5

Bitfield<23, 20> gem5::RiscvISA::ssv5

Definition at line 169 of file pra_constants.hh.

ssv6

Bitfield<27, 24> gem5::RiscvISA::ssv6

Definition at line 168 of file pra_constants.hh.

ssv7

gem5::RiscvISA::ssv7

Definition at line 167 of file pra_constants.hh.

StackPointerReg

auto & gem5::RiscvISA::StackPointerReg = int_reg::Sp

Definition at line 141 of file int.hh.

Referenced by gem5::RiscvLinux32::archClone(), and gem5::RiscvLinux64::archClone().

StackRegs

RegId gem5::RiscvISA::StackRegs[]

inlineconstexpr

Initial value:

= {
  int_reg::S0, int_reg::S1, int_reg::S2, int_reg::S3,
  int_reg::S4, int_reg::S5, int_reg::S6, int_reg::S7,
}

Definition at line 159 of file int.hh.

STATUS_FS_MASK

const RegVal gem5::RiscvISA::STATUS_FS_MASK = 3ULL << FS_OFFSET

Definition at line 1512 of file misc.hh.

STATUS_GVA_MASK

const RegVal gem5::RiscvISA::STATUS_GVA_MASK = 1LL << 38

Definition at line 1502 of file misc.hh.

STATUS_MBE_MASK

const RegVal gem5::RiscvISA::STATUS_MBE_MASK[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << MBE_OFFSET[RV32],
    [RV64] = 1ULL << MBE_OFFSET[RV64],
}

Definition at line 1492 of file misc.hh.

STATUS_MIE_MASK

const RegVal gem5::RiscvISA::STATUS_MIE_MASK = 1ULL << 3

Definition at line 1519 of file misc.hh.

STATUS_MPIE_MASK

const RegVal gem5::RiscvISA::STATUS_MPIE_MASK = 1ULL << 7

Definition at line 1516 of file misc.hh.

STATUS_MPP_MASK

const RegVal gem5::RiscvISA::STATUS_MPP_MASK = 3ULL << 11

Definition at line 1513 of file misc.hh.

STATUS_MPRV_MASK

const RegVal gem5::RiscvISA::STATUS_MPRV_MASK = 1ULL << 17

Definition at line 1510 of file misc.hh.

STATUS_MPV_MASK

const RegVal gem5::RiscvISA::STATUS_MPV_MASK = 1LL << 39

Definition at line 1501 of file misc.hh.

STATUS_MXR_MASK

const RegVal gem5::RiscvISA::STATUS_MXR_MASK = 1ULL << 19

Definition at line 1508 of file misc.hh.

STATUS_SBE_MASK

const RegVal gem5::RiscvISA::STATUS_SBE_MASK[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << SBE_OFFSET[RV32],
    [RV64] = 1ULL << SBE_OFFSET[RV64],
}

Definition at line 1496 of file misc.hh.

STATUS_SD_MASKS

const RegVal gem5::RiscvISA::STATUS_SD_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << ((sizeof(uint32_t) * 8) - 1),
    [RV64] = 1ULL << ((sizeof(uint64_t) * 8) - 1),
}

Definition at line 1488 of file misc.hh.

STATUS_SIE_MASK

const RegVal gem5::RiscvISA::STATUS_SIE_MASK = 1ULL << 1

Definition at line 1520 of file misc.hh.

STATUS_SPIE_MASK

const RegVal gem5::RiscvISA::STATUS_SPIE_MASK = 1ULL << 5

Definition at line 1518 of file misc.hh.

STATUS_SPP_MASK

const RegVal gem5::RiscvISA::STATUS_SPP_MASK = 1ULL << 8

Definition at line 1515 of file misc.hh.

STATUS_SUM_MASK

const RegVal gem5::RiscvISA::STATUS_SUM_MASK = 1ULL << 18

Definition at line 1509 of file misc.hh.

STATUS_SXL_MASK

const RegVal gem5::RiscvISA::STATUS_SXL_MASK = 3ULL << SXL_OFFSET

Definition at line 1503 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

STATUS_TSR_MASK

const RegVal gem5::RiscvISA::STATUS_TSR_MASK = 1ULL << 22

Definition at line 1505 of file misc.hh.

STATUS_TVM_MASK

const RegVal gem5::RiscvISA::STATUS_TVM_MASK = 1ULL << 20

Definition at line 1507 of file misc.hh.

STATUS_TW_MASK

const RegVal gem5::RiscvISA::STATUS_TW_MASK = 1ULL << 21

Definition at line 1506 of file misc.hh.

STATUS_UBE_MASK

const RegVal gem5::RiscvISA::STATUS_UBE_MASK = 1ULL << 6

Definition at line 1517 of file misc.hh.

STATUS_UXL_MASK

const RegVal gem5::RiscvISA::STATUS_UXL_MASK = 3ULL << UXL_OFFSET

Definition at line 1504 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

STATUS_VS_MASK

const RegVal gem5::RiscvISA::STATUS_VS_MASK = 3ULL << VS_OFFSET

Definition at line 1514 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

STATUS_XS_MASK

const RegVal gem5::RiscvISA::STATUS_XS_MASK = 3ULL << 15

Definition at line 1511 of file misc.hh.

sti

Bitfield<5> gem5::RiscvISA::sti

Definition at line 1432 of file misc.hh.

STI_MASK

const RegVal gem5::RiscvISA::STI_MASK = 1ULL << 5

Definition at line 1638 of file misc.hh.

su

Bitfield<15, 12> gem5::RiscvISA::su

Definition at line 256 of file pra_constants.hh.

succ

Bitfield<23, 20> gem5::RiscvISA::succ

Definition at line 90 of file types.hh.

Referenced by gem5::RequestPort::sendTimingReq(), and gem5::ResponsePort::sendTimingResp().

sum

Bitfield<18> gem5::RiscvISA::sum

Definition at line 1346 of file misc.hh.

Referenced by gem5::networking::__tu_cksum(), gem5::networking::__tu_cksum6(), gem5::PowerISA::IntArithOp::add(), gem5::PowerISA::IntArithOp::add(), gem5::X86ISA::ACPI::apic_checksum(), gem5::RiscvISA::TLB::checkPermissions(), gem5::networking::cksum(), gem5::ruby::Throttle::getTotalLinkBandwidth(), gem5::TrafficGen::parseConfig(), gem5::popCount(), gem5::ruby::garnet::GarnetNetwork::regStats(), gem5::ruby::SimpleNetwork::regStats(), and TEST().

sumop

Bitfield<24, 20> gem5::RiscvISA::sumop

Definition at line 165 of file types.hh.

SV39_LEVEL_BITS

const Addr gem5::RiscvISA::SV39_LEVEL_BITS = 9

Definition at line 63 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::guestToHostPage(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalkGStage(), and gem5::RiscvISA::Walker::WalkerState::walkGStage().

SV39_LEVELS

const Addr gem5::RiscvISA::SV39_LEVELS = 3

Definition at line 62 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::walkGStage(), gem5::RiscvISA::Walker::WalkerState::walkOneStage(), and gem5::RiscvISA::Walker::WalkerState::walkTwoStage().

SV39_VADDR_BITS

const Addr gem5::RiscvISA::SV39_VADDR_BITS = 39

Definition at line 61 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::walkOneStage(), and gem5::RiscvISA::Walker::WalkerState::walkTwoStage().

SV39_XLEN

const Addr gem5::RiscvISA::SV39_XLEN = 64

Definition at line 60 of file pagetable.hh.

SV39X4_WIDENED_BITS

const Addr gem5::RiscvISA::SV39X4_WIDENED_BITS = 2

Definition at line 64 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::setupWalk(), and gem5::RiscvISA::Walker::WalkerState::walkGStage().

sx

Bitfield<6> gem5::RiscvISA::sx

Definition at line 135 of file pra_constants.hh.

sxl

Bitfield<35, 34> gem5::RiscvISA::sxl

Definition at line 1339 of file misc.hh.

SXL_OFFSET

const off_t gem5::RiscvISA::SXL_OFFSET = 34

Definition at line 1469 of file misc.hh.

SyscallNumReg

auto & gem5::RiscvISA::SyscallNumReg = int_reg::A7

Definition at line 145 of file int.hh.

Referenced by gem5::RiscvISA::EmuLinux::syscall().

ta

Bitfield<19, 16> gem5::RiscvISA::ta

Definition at line 255 of file pra_constants.hh.

ThreadPointerReg

auto & gem5::RiscvISA::ThreadPointerReg = int_reg::Tp

Definition at line 142 of file int.hh.

Referenced by gem5::RiscvLinux32::archClone(), and gem5::RiscvLinux64::archClone().

ti

Bitfield<30> gem5::RiscvISA::ti

Definition at line 179 of file pra_constants.hh.

tl

Bitfield< 0 > gem5::RiscvISA::tl

Definition at line 254 of file pra_constants.hh.

ts

Bitfield< 27, 24 > gem5::RiscvISA::ts

Definition at line 118 of file pra_constants.hh.

tsr

Bitfield<22> gem5::RiscvISA::tsr

Definition at line 1342 of file misc.hh.

tu

Bitfield<30, 28> gem5::RiscvISA::tu

Definition at line 252 of file pra_constants.hh.

tvm

Bitfield<20> gem5::RiscvISA::tvm

Definition at line 1344 of file misc.hh.

tw

Bitfield<21> gem5::RiscvISA::tw

Definition at line 1343 of file misc.hh.

u

Bitfield< 3 > gem5::RiscvISA::u

Definition at line 76 of file pagetable.hh.

ube

Bitfield<6> gem5::RiscvISA::ube

Definition at line 1354 of file misc.hh.

uimm_vsetivli

Bitfield<19, 15> gem5::RiscvISA::uimm_vsetivli

Definition at line 180 of file types.hh.

Referenced by gem5::RiscvISA::VConfOp::VConfOp().

ujimmbit11

Bitfield<20> gem5::RiscvISA::ujimmbit11

Definition at line 104 of file types.hh.

ujimmbits10to1

Bitfield<30, 21> gem5::RiscvISA::ujimmbits10to1

Definition at line 103 of file types.hh.

ujimmbits19to12

Bitfield<19, 12> gem5::RiscvISA::ujimmbits19to12

Definition at line 105 of file types.hh.

um

Bitfield<4> gem5::RiscvISA::um

Definition at line 138 of file pra_constants.hh.

ux

Bitfield<5> gem5::RiscvISA::ux

Definition at line 136 of file pra_constants.hh.

Referenced by sat_add(), and sat_sub().

uxl

Bitfield<33, 32> gem5::RiscvISA::uxl

Definition at line 1340 of file misc.hh.

UXL_OFFSET

const off_t gem5::RiscvISA::UXL_OFFSET = 32

Definition at line 1471 of file misc.hh.

v

Bitfield< 1 > gem5::RiscvISA::v

Definition at line 81 of file pagetable.hh.

Referenced by boxF16(), boxF32(), f16(), f32(), f64(), gem5::RiscvISA::PCState::new_vconf(), unboxF16(), unboxF32(), gem5::RiscvISA::PCState::vl(), and gem5::RiscvISA::PCState::vtype().

vaddr

gem5::RiscvISA::vaddr

Definition at line 278 of file pra_constants.hh.

Referenced by gem5::RiscvISA::AddressFault::AddressFault(), gem5::RiscvISA::BasePMAChecker::check(), gem5::RiscvISA::PMAChecker::check(), gem5::RiscvISA::PMAChecker::checkPAddrAlignment(), gem5::RiscvISA::TLB::checkPermissions(), gem5::RiscvISA::PMP::createAddrfault(), gem5::RiscvISA::PMAChecker::createMisalignFault(), gem5::RiscvISA::TLB::createPagefault(), gem5::RiscvISA::TLB::demapPage(), gem5::RiscvISA::TLB::doTranslate(), EndBitUnion(), gem5::RiscvISA::TLB::getTableWalkerPort(), gem5::RiscvISA::MMU::getValidAddr(), gem5::RiscvISA::TLB::getValidAddr(), getVPNFromVAddr(), gem5::RiscvISA::Walker::WalkerState::guestToHostPage(), gem5::RiscvISA::TLB::hiddenTranslateWithTLB(), gem5::RiscvISA::PMP::pmpCheck(), gem5::RiscvISA::Walker::WalkerState::recvPacket(), gem5::RiscvISA::TLB::remove(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::startWalkWrapper(), gem5::RiscvISA::TLB::translate(), gem5::RiscvISA::Walker::WalkerState::walk(), gem5::RiscvISA::Walker::WalkerState::walkOneStage(), and gem5::RiscvISA::Walker::WalkerState::walkTwoStage().

vd

Bitfield<11, 7> gem5::RiscvISA::vd

Definition at line 169 of file types.hh.

Referenced by gem5::RiscvISA::VPinVdMicroInst::execute(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::VoltageDomain::VoltageDomainStats::VoltageDomainStats(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

vecimm

Bitfield<19, 15> gem5::RiscvISA::vecimm

Definition at line 171 of file types.hh.

VecMemInternalReg0

const int gem5::RiscvISA::VecMemInternalReg0 = NumVecStandardRegs

Definition at line 67 of file vector.hh.

Referenced by gem5::RiscvISA::VCpyVsMicroInst::VCpyVsMicroInst(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(), gem5::RiscvISA::VMaskMergeMicroInst::VMaskMergeMicroInst(), and gem5::RiscvISA::VsSegIntrlvMicroInst::VsSegIntrlvMicroInst().

vecRegClass

RegClass gem5::RiscvISA::vecRegClass

inlineconstexpr

Initial value:

=
    RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
        ops(vecRegClassOps).
        regType<VecRegContainer>()

Definition at line 71 of file vector.hh.

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), gem5::RiscvISA::VCpyVsMicroInst::execute(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::RiscvISA::VPinVdMicroInst::execute(), gem5::RiscvISA::VsSegIntrlvMicroInst::execute(), gem5::RiscvISA::ISA::ISA(), gem5::RiscvISA::VCpyVsMicroInst::VCpyVsMicroInst(), gem5::RiscvISA::VlFFTrimVlMicroOp::VlFFTrimVlMicroOp(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(), gem5::RiscvISA::VMaskMergeMicroInst::VMaskMergeMicroInst(), gem5::RiscvISA::VPinVdMicroInst::VPinVdMicroInst(), and gem5::RiscvISA::VsSegIntrlvMicroInst::VsSegIntrlvMicroInst().

vecRegClassOps

TypedRegClassOps<RiscvISA::VecRegContainer> gem5::RiscvISA::vecRegClassOps

inlinestatic

Definition at line 69 of file vector.hh.

VecRegNames

const std::vector<std::string> gem5::RiscvISA::VecRegNames

Initial value:

= {
    "v0",   "v1",   "v2",   "v3",   "v4",   "v5",   "v6",   "v7",
    "v8",   "v9",   "v10",  "v11",  "v12",  "v13",  "v14",  "v15",
    "v16",  "v17",  "v18",  "v19",  "v20",  "v21",  "v22",  "v23",
    "v24",  "v25",  "v26",  "v27",  "v28",  "v29",  "v30",  "v31",
    "vtmp0", "vtmp1", "vtmp2", "vtmp3", "vtmp4", "vtmp5", "vtmp6", "vtmp7"
}

Definition at line 58 of file vector.hh.

Referenced by registerName().

veic

Bitfield<6> gem5::RiscvISA::veic

Definition at line 268 of file pra_constants.hh.

vfunct2

Bitfield<26, 25> gem5::RiscvISA::vfunct2

Definition at line 159 of file types.hh.

vfunct3

Bitfield<27, 25> gem5::RiscvISA::vfunct3

Definition at line 158 of file types.hh.

vfunct5

Bitfield<31, 27> gem5::RiscvISA::vfunct5

Definition at line 157 of file types.hh.

vfunct6

Bitfield<31, 26> gem5::RiscvISA::vfunct6

Definition at line 156 of file types.hh.

vgein

Bitfield<17, 12> gem5::RiscvISA::vgein

Definition at line 1367 of file misc.hh.

vi

Bitfield<3> gem5::RiscvISA::vi

Definition at line 228 of file pra_constants.hh.

vill

Bitfield<40> gem5::RiscvISA::vill

Definition at line 64 of file types.hh.

Referenced by BitUnion64(), and checked_vtype().

vint

Bitfield<5> gem5::RiscvISA::vint

Definition at line 269 of file pra_constants.hh.

vl

Bitfield<57, 41> gem5::RiscvISA::vl

Definition at line 63 of file types.hh.

Referenced by gem5::RiscvISA::VlFFTrimVlMicroOp::branchTarget(), and gem5::RiscvISA::VlFFTrimVlMicroOp::calcVl().

vlmul

Bitfield< 34, 32 > gem5::RiscvISA::vlmul

Definition at line 82 of file vector.hh.

Referenced by checked_vtype(), getVflmul(), and SubBitUnion().

vm

Bitfield<25> gem5::RiscvISA::vm

Definition at line 163 of file types.hh.

vma

Bitfield<7> gem5::RiscvISA::vma

Definition at line 79 of file vector.hh.

Referenced by gem5::GPUComputeDriver::deallocateGpuVma(), gem5::MemState::fixupFault(), gem5::RiscvISA::VConfOp::generateZimmDisassembly(), gem5::MemState::isUnmapped(), gem5::MemState::printVmaList(), gem5::MemState::remapRegion(), gem5::MemState::serialize(), gem5::GPUComputeDriver::setMtype(), SubBitUnion(), and gem5::MemState::unmapRegion().

vpn2

Bitfield<39, 13> gem5::RiscvISA::vpn2

Definition at line 100 of file pra_constants.hh.

vpn2x

Bitfield<12, 11> gem5::RiscvISA::vpn2x

Definition at line 101 of file pra_constants.hh.

vs

Bitfield< 10, 9 > gem5::RiscvISA::vs

Definition at line 149 of file pra_constants.hh.

Referenced by elem_mask(), elem_mask_vseg(), gem5::RiscvISA::VCpyVsMicroInst::execute(), and gem5::RiscvISA::VPinVdMicroInst::execute().

vs1

Bitfield<19, 15> gem5::RiscvISA::vs1

Definition at line 168 of file types.hh.

vs2

Bitfield<24, 20> gem5::RiscvISA::vs2

Definition at line 167 of file types.hh.

vs3

Bitfield<11, 7> gem5::RiscvISA::vs3

Definition at line 170 of file types.hh.

VS_DELEGABLE_EXCPS

const RegVal gem5::RiscvISA::VS_DELEGABLE_EXCPS

Initial value:

= DELEGABLE_EXCPS &
    ~((1ULL << ECALL_SUPER) |
    (1ULL << ECALL_VIRTUAL_SUPER) |
    (1ULL << ECALL_MACHINE) |
    (1ULL << INST_GUEST_PAGE) |
    (1ULL << LOAD_GUEST_PAGE) |
    (1ULL << VIRTUAL_INST) |
    (1ULL << STORE_GUEST_PAGE))

Definition at line 181 of file fault_codes.hh.

VS_OFFSET

const off_t gem5::RiscvISA::VS_OFFSET = 9

Definition at line 1473 of file misc.hh.

vsbe

Bitfield<5> gem5::RiscvISA::vsbe

Definition at line 1372 of file misc.hh.

vsei

Bitfield<10> gem5::RiscvISA::vsei

Definition at line 1428 of file misc.hh.

VSEI_MASK

const RegVal gem5::RiscvISA::VSEI_MASK = 1ULL << 10

Definition at line 1634 of file misc.hh.

vsew

Bitfield< 37, 35 > gem5::RiscvISA::vsew

Definition at line 81 of file vector.hh.

Referenced by checked_vtype(), getSew(), SubBitUnion(), and vtype_VLMAX().

VSI_MASK

const RegVal gem5::RiscvISA::VSI_MASK[enums::Num_PrivilegeModeSet]

Initial value:

= {
    [enums::M] = LOCAL_MASK,
    [enums::MU] = LOCAL_MASK,
    [enums::MSU] = LOCAL_MASK,
    [enums::MHSU] = LOCAL_MASK | VSEI_MASK | VSTI_MASK | VSSI_MASK,
}

Definition at line 1671 of file misc.hh.

vssi

Bitfield<2> gem5::RiscvISA::vssi

Definition at line 1434 of file misc.hh.

VSSI_MASK

const RegVal gem5::RiscvISA::VSSI_MASK = 1ULL << 2

Definition at line 1640 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::writeCSR().

vsti

Bitfield<6> gem5::RiscvISA::vsti

Definition at line 1431 of file misc.hh.

VSTI_MASK

const RegVal gem5::RiscvISA::VSTI_MASK = 1ULL << 6

Definition at line 1637 of file misc.hh.

vsxl

gem5::RiscvISA::vsxl

Definition at line 1363 of file misc.hh.

VSXL_OFFSET

const off_t gem5::RiscvISA::VSXL_OFFSET = 32

Definition at line 1470 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::readMiscReg().

vta

Bitfield< 38 > gem5::RiscvISA::vta

Definition at line 80 of file vector.hh.

Referenced by gem5::RiscvISA::VConfOp::generateZimmDisassembly(), and SubBitUnion().

vtsr

Bitfield<22> gem5::RiscvISA::vtsr

Definition at line 1364 of file misc.hh.

vtvm

Bitfield<20> gem5::RiscvISA::vtvm

Definition at line 1366 of file misc.hh.

vtw

Bitfield<21> gem5::RiscvISA::vtw

Definition at line 1365 of file misc.hh.

vtype8

Bitfield<7, 0> gem5::RiscvISA::vtype8

Definition at line 78 of file vector.hh.

Referenced by EndSubBitUnion(), SubBitUnion(), gem5::RiscvISA::VectorMacroInst::VectorMacroInst(), gem5::RiscvISA::VectorMicroInst::VectorMicroInst(), and gem5::RiscvISA::VectorNonSplitInst::VectorNonSplitInst().

w

Bitfield< 30 > gem5::RiscvISA::w

Definition at line 79 of file pagetable.hh.

Referenced by EndBitUnion(), and EndBitUnion().

width

Bitfield<14, 12> gem5::RiscvISA::width

Definition at line 166 of file types.hh.

Referenced by gem5::RiscvISA::VectorMemMacroInst::VectorMemMacroInst(), gem5::RiscvISA::VectorMemMicroInst::VectorMemMicroInst(), and width_EEW().

wired

gem5::RiscvISA::wired

Definition at line 89 of file pra_constants.hh.

wp

Bitfield<22> gem5::RiscvISA::wp

Definition at line 185 of file pra_constants.hh.

wpri_1

gem5::RiscvISA::wpri_1

Definition at line 1442 of file misc.hh.

wpri_2

Bitfield<31,8> gem5::RiscvISA::wpri_2

Definition at line 1444 of file misc.hh.

wpri_3

Bitfield<3,1> gem5::RiscvISA::wpri_3

Definition at line 1448 of file misc.hh.

wr

Bitfield<3> gem5::RiscvISA::wr

Definition at line 244 of file pra_constants.hh.

x

Bitfield<3> gem5::RiscvISA::x

Definition at line 78 of file pagetable.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64dsm(), _rvk_emu_aes64esm(), _rvk_emu_aes_fwd_mc_32(), _rvk_emu_aes_fwd_mc_8(), _rvk_emu_aes_inv_mc_32(), _rvk_emu_aes_inv_mc_8(), _rvk_emu_aes_xtime(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), _rvk_emu_sha256sum1(), _rvk_emu_shfl_32(), _rvk_emu_shuffle32_stage(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_unshfl_32(), gem5::o3::LSQUnit::checkSnoop(), gem5::o3::LSQUnit::commitStores(), gem5::FreeList< T >::Range::contains(), gem5::CopyEngine::CopyEngine(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::prefetch::BOP::DelayQueueEntry::DelayQueueEntry(), gem5::SparcISA::TLB::demapAll(), gem5::SparcISA::TLB::demapContext(), gem5::SparcISA::TLB::dumpAll(), gem5::IGbE::DescCache< T >::fetchComplete(), gem5::Float16::Float16(), gem5::Float16::Float16(), gem5::floorLog2(), gem5::SparcISA::TLB::flushAll(), gem5::ArmISA::fp16_add(), gem5::ArmISA::fp16_div(), gem5::ArmISA::fp16_halved_add(), gem5::ArmISA::fp16_mul(), gem5::ArmISA::fp16_muladd(), gem5::ArmISA::fp16_sqrt(), gem5::ArmISA::fp16_unpack(), gem5::ArmISA::fp32_add(), gem5::ArmISA::fp32_div(), gem5::ArmISA::fp32_mul(), gem5::ArmISA::fp32_muladd(), gem5::ArmISA::fp32_muladdh(), gem5::ArmISA::fp32_sqrt(), gem5::ArmISA::fp32_unpack(), gem5::ArmISA::fp64_add(), gem5::ArmISA::fp64_div(), gem5::ArmISA::fp64_mul(), gem5::ArmISA::fp64_muladd(), gem5::ArmISA::fp64_sqrt(), gem5::ArmISA::fp64_unpack(), gem5::ArmISA::fplibCompareEQ(), gem5::ArmISA::fplibCompareEQ(), gem5::ArmISA::fplibCompareEQ(), gem5::ArmISA::fplibCompareGE(), gem5::ArmISA::fplibCompareGE(), gem5::ArmISA::fplibCompareGE(), gem5::ArmISA::fplibCompareGT(), gem5::ArmISA::fplibCompareGT(), gem5::ArmISA::fplibCompareGT(), gem5::ArmISA::fplibCompareUN(), gem5::ArmISA::fplibCompareUN(), gem5::ArmISA::fplibCompareUN(), gem5::ArmISA::fplibMax(), gem5::ArmISA::fplibMax(), gem5::ArmISA::fplibMax(), gem5::ArmISA::fplibMin(), gem5::ArmISA::fplibMin(), gem5::ArmISA::fplibMin(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRoundIntN(), gem5::ArmISA::fplibRoundIntN(), gem5::ArmISA::FpOp::fpSqrt(), gem5::ArmISA::FpOp::fpSqrt(), gem5::ArmISA::FPToFixed_16(), gem5::ArmISA::FPToFixed_32(), gem5::ArmISA::FPToFixed_64(), fsgnj(), fsgnj16(), fsgnj32(), fsgnj64(), gem5::getFpRound(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::LOCAL::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::GicV2::GicV2(), gem5::Gicv2m::Gicv2m(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::stl_helpers::hash_impl::hash_refine(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hashPC(), gem5::branch_prediction::MultiperspectivePerceptron::insert(), gem5::SparcISA::TLB::insert(), gem5::prefetch::BOP::insertIntoDelayQueue(), gem5::Iob::Iob(), gem5::ArmISA::lsl16(), gem5::ArmISA::lsl32(), gem5::ArmISA::lsl64(), gem5::ArmISA::lsr16(), gem5::ArmISA::lsr32(), gem5::ArmISA::lsr64(), gem5::ArmISA::modeConv(), gem5::ps2::TouchKit::mouseAt(), gem5::VncMouse::mouseAt(), gem5::BasePixelPump::onUnderrun(), gem5::HDLcd::PixelPump::onUnderrun(), gem5::FrameBuffer::pixel(), gem5::FrameBuffer::pixel(), gem5::FreeList< T >::Range::precedes(), gem5::SparcISA::SparcStaticInst::printRegArray(), gem5::RangeAddrMapper::RangeAddrMapper(), gem5::GicV2::readCpu(), gem5::SparcISA::ISA::readFSReg(), gem5::IGbE::DescCache< T >::reset(), gem5::ArmISA::Crypto::ror(), gem5::RiscvISA::RiscvStaticInst::rvExt(), gem5::RiscvISA::RiscvStaticInst::rvSext(), gem5::RiscvISA::RiscvStaticInst::rvZext(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::MMU::s2PermBits64(), sat_add(), sat_addu(), sat_sub(), sat_subu(), gem5::Shader::ScheduleAdd(), gem5::VncServer::sendFrameBufferUpdate(), gem5::CopyEngine::serialize(), gem5::IGbE::DescCache< T >::serialize(), gem5::Iob::serialize(), gem5::Pl111::serialize(), gem5::SparcISA::TLB::serialize(), gem5::VncServer::setEncodings(), gem5::GicV2::softInt(), gem5::swap_byte(), gem5::swap_byte16(), gem5::swap_byte32(), gem5::swap_byte64(), gem5::System::System(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), gem5::SparcISA::TLB::TLB(), gem5::SparcISA::TLB::translateFunctional(), gem5::CopyEngine::unserialize(), gem5::IGbE::DescCache< T >::unserialize(), gem5::Iob::unserialize(), gem5::Pl111::unserialize(), gem5::SparcISA::TLB::unserialize(), gem5::GicV2::updateIntState(), gem5::VGic::VGic(), gem5::IGbE::DescCache< T >::wbComplete(), gem5::BmpWriter::write(), gem5::PngWriter::write(), gem5::IGbE::DescCache< T >::writeback1(), gem5::CopyEngine::~CopyEngine(), gem5::GicV2::~GicV2(), and gem5::VGic::~VGic().

xs

Bitfield<16, 15> gem5::RiscvISA::xs

Definition at line 1348 of file misc.hh.

zimm_vsetivli

Bitfield<29, 20> gem5::RiscvISA::zimm_vsetivli

Definition at line 179 of file types.hh.

Referenced by gem5::RiscvISA::VConfOp::VConfOp().

zimm_vsetvli

Bitfield<30, 20> gem5::RiscvISA::zimm_vsetvli

Definition at line 176 of file types.hh.

Referenced by gem5::RiscvISA::VConfOp::VConfOp().