gem5::VegaISA::Inst_SOP1 Class Reference

#include <op_encodings.hh>

Inheritance diagram for gem5::VegaISA::Inst_SOP1:

Public Member Functions
	Inst_SOP1 (InFmt_SOP1 *, const std::string &opcode)
	~Inst_SOP1 ()
int	instSize () const override
void	generateDisassembly () override
void	initOperandInfo () override
Public Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
	VEGAGPUStaticInst (const std::string &opcode)
	~VEGAGPUStaticInst ()
void	generateDisassembly () override
bool	isFlatScratchRegister (int opIdx) override
bool	isExecMaskRegister (int opIdx) override
void	initOperandInfo () override
int	getOperandSize (int opIdx) override
int	coalescerTokenCount () const override
	Return the number of tokens needed by the coalescer.
ScalarRegU32	srcLiteral () const override
Public Member Functions inherited from gem5::GPUStaticInst
	GPUStaticInst (const std::string &opcode)
virtual	~GPUStaticInst ()
void	instAddr (int inst_addr)
int	instAddr () const
int	nextInstAddr () const
void	instNum (int num)
int	instNum ()
void	ipdInstNum (int num)
int	ipdInstNum () const
void	initDynOperandInfo (Wavefront *wf, ComputeUnit *cu)
virtual void	execute (GPUDynInstPtr gpuDynInst)=0
const std::string &	disassemble ()
virtual int	getNumOperands ()=0
virtual int	numDstRegOperands ()=0
virtual int	numSrcRegOperands ()=0
int	numSrcVecOperands ()
int	numDstVecOperands ()
int	numSrcVecDWords ()
int	numDstVecDWords ()
int	numSrcScalarOperands ()
int	numDstScalarOperands ()
int	numSrcScalarDWords ()
int	numDstScalarDWords ()
int	maxOperandSize ()
bool	isALU () const
bool	isBranch () const
bool	isCondBranch () const
bool	isNop () const
bool	isReturn () const
bool	isEndOfKernel () const
bool	isKernelLaunch () const
bool	isSDWAInst () const
bool	isDPPInst () const
bool	isUnconditionalJump () const
bool	isSpecialOp () const
bool	isWaitcnt () const
bool	isSleep () const
bool	isBarrier () const
bool	isMemSync () const
bool	isMemRef () const
bool	isFlat () const
bool	isFlatGlobal () const
bool	isFlatScratch () const
bool	isLoad () const
bool	isStore () const
bool	isAtomic () const
bool	isAtomicNoRet () const
bool	isAtomicRet () const
bool	isScalar () const
bool	readsSCC () const
bool	writesSCC () const
bool	readsVCC () const
bool	writesVCC () const
bool	readsEXEC () const
bool	writesEXEC () const
bool	readsMode () const
bool	writesMode () const
bool	ignoreExec () const
bool	isAtomicAnd () const
bool	isAtomicOr () const
bool	isAtomicXor () const
bool	isAtomicCAS () const
bool	isAtomicExch () const
bool	isAtomicAdd () const
bool	isAtomicSub () const
bool	isAtomicInc () const
bool	isAtomicDec () const
bool	isAtomicMax () const
bool	isAtomicMin () const
bool	isArgLoad () const
bool	isGlobalMem () const
bool	isLocalMem () const
bool	isArgSeg () const
bool	isGlobalSeg () const
bool	isGroupSeg () const
bool	isKernArgSeg () const
bool	isPrivateSeg () const
bool	isReadOnlySeg () const
bool	isSpillSeg () const
bool	isGloballyCoherent () const
	Coherence domain of a memory instruction.
bool	isSystemCoherent () const
bool	isI8 () const
bool	isF16 () const
bool	isF32 () const
bool	isF64 () const
bool	isFMA () const
bool	isMAC () const
bool	isMAD () const
bool	isMFMA () const
bool	hasNoAddr () const
virtual void	initiateAcc (GPUDynInstPtr gpuDynInst)
virtual void	completeAcc (GPUDynInstPtr gpuDynInst)
virtual uint32_t	getTargetPc ()
void	setFlag (Flags flag)
const std::string &	opcode () const
const std::vector< OperandInfo > &	srcOperands () const
const std::vector< OperandInfo > &	dstOperands () const
const std::vector< OperandInfo > &	srcVecRegOperands () const
const std::vector< OperandInfo > &	dstVecRegOperands () const
const std::vector< OperandInfo > &	srcScalarRegOperands () const
const std::vector< OperandInfo > &	dstScalarRegOperands () const

Protected Attributes
InFmt_SOP1	instData
InstFormat	extData
uint32_t	varSize
Protected Attributes inherited from gem5::VegaISA::VEGAGPUStaticInst
ScalarRegU32	_srcLiteral
	if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here
Protected Attributes inherited from gem5::GPUStaticInst
const std::string	_opcode
std::string	disassembly
int	_instNum
int	_instAddr
std::vector< OperandInfo >	srcOps
std::vector< OperandInfo >	dstOps

Private Member Functions
bool	hasSecondDword (InFmt_SOP1 *)

Additional Inherited Members
Public Types inherited from gem5::GPUStaticInst
enum	OpType { SRC_VEC , SRC_SCALAR , DST_VEC , DST_SCALAR }
typedef int(RegisterManager::*	MapRegFn) (Wavefront *, int)
Public Attributes inherited from gem5::GPUStaticInst
enums::StorageClassType	executed_as
Static Public Attributes inherited from gem5::GPUStaticInst
static uint64_t	dynamic_id_count
Protected Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
void	panicUnimplemented () const

Detailed Description

Definition at line 117 of file op_encodings.hh.

Constructor & Destructor Documentation

Inst_SOP1()

gem5::VegaISA::Inst_SOP1::Inst_SOP1	(	InFmt_SOP1 *	iFmt,
		const std::string &	opcode )

Definition at line 223 of file op_encodings.cc.

References gem5::VegaISA::VEGAGPUStaticInst::_srcLiteral, extData, hasSecondDword(), instData, gem5::GPUStaticInst::opcode(), gem5::GPUStaticInst::setFlag(), varSize, and gem5::VegaISA::VEGAGPUStaticInst::VEGAGPUStaticInst().

Referenced by gem5::VegaISA::Inst_SOP1__S_ABS_I32::Inst_SOP1__S_ABS_I32(), gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64::Inst_SOP1__S_AND_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64::Inst_SOP1__S_ANDN2_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32::Inst_SOP1__S_BCNT0_I32_B32(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64::Inst_SOP1__S_BCNT0_I32_B64(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32::Inst_SOP1__S_BCNT1_I32_B32(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64::Inst_SOP1__S_BCNT1_I32_B64(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B32::Inst_SOP1__S_BITSET0_B32(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B64::Inst_SOP1__S_BITSET0_B64(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B32::Inst_SOP1__S_BITSET1_B32(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B64::Inst_SOP1__S_BITSET1_B64(), gem5::VegaISA::Inst_SOP1__S_BREV_B32::Inst_SOP1__S_BREV_B32(), gem5::VegaISA::Inst_SOP1__S_BREV_B64::Inst_SOP1__S_BREV_B64(), gem5::VegaISA::Inst_SOP1__S_CBRANCH_JOIN::Inst_SOP1__S_CBRANCH_JOIN(), gem5::VegaISA::Inst_SOP1__S_CMOV_B32::Inst_SOP1__S_CMOV_B32(), gem5::VegaISA::Inst_SOP1__S_CMOV_B64::Inst_SOP1__S_CMOV_B64(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32::Inst_SOP1__S_FF0_I32_B32(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64::Inst_SOP1__S_FF0_I32_B64(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32::Inst_SOP1__S_FF1_I32_B32(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64::Inst_SOP1__S_FF1_I32_B64(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32::Inst_SOP1__S_FLBIT_I32(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32::Inst_SOP1__S_FLBIT_I32_B32(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64::Inst_SOP1__S_FLBIT_I32_B64(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64::Inst_SOP1__S_FLBIT_I32_I64(), gem5::VegaISA::Inst_SOP1__S_GETPC_B64::Inst_SOP1__S_GETPC_B64(), gem5::VegaISA::Inst_SOP1__S_MOV_B32::Inst_SOP1__S_MOV_B32(), gem5::VegaISA::Inst_SOP1__S_MOV_B64::Inst_SOP1__S_MOV_B64(), gem5::VegaISA::Inst_SOP1__S_MOV_FED_B32::Inst_SOP1__S_MOV_FED_B32(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32::Inst_SOP1__S_MOVRELD_B32(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64::Inst_SOP1__S_MOVRELD_B64(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32::Inst_SOP1__S_MOVRELS_B32(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64::Inst_SOP1__S_MOVRELS_B64(), gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64::Inst_SOP1__S_NAND_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64::Inst_SOP1__S_NOR_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_NOT_B32::Inst_SOP1__S_NOT_B32(), gem5::VegaISA::Inst_SOP1__S_NOT_B64::Inst_SOP1__S_NOT_B64(), gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64::Inst_SOP1__S_OR_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64::Inst_SOP1__S_ORN2_SAVEEXEC_B64(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32::Inst_SOP1__S_QUADMASK_B32(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64::Inst_SOP1__S_QUADMASK_B64(), gem5::VegaISA::Inst_SOP1__S_RFE_B64::Inst_SOP1__S_RFE_B64(), gem5::VegaISA::Inst_SOP1__S_SET_GPR_IDX_IDX::Inst_SOP1__S_SET_GPR_IDX_IDX(), gem5::VegaISA::Inst_SOP1__S_SETPC_B64::Inst_SOP1__S_SETPC_B64(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16::Inst_SOP1__S_SEXT_I32_I16(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8::Inst_SOP1__S_SEXT_I32_I8(), gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64::Inst_SOP1__S_SWAPPC_B64(), gem5::VegaISA::Inst_SOP1__S_WQM_B32::Inst_SOP1__S_WQM_B32(), gem5::VegaISA::Inst_SOP1__S_WQM_B64::Inst_SOP1__S_WQM_B64(), gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64::Inst_SOP1__S_XNOR_SAVEEXEC_B64(), and gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64::Inst_SOP1__S_XOR_SAVEEXEC_B64().

~Inst_SOP1()

gem5::VegaISA::Inst_SOP1::~Inst_SOP1

(

)

Definition at line 240 of file op_encodings.cc.

Member Function Documentation

generateDisassembly()

void gem5::VegaISA::Inst_SOP1::generateDisassembly ( )

overridevirtual

Implements gem5::GPUStaticInst.

Definition at line 294 of file op_encodings.cc.

References gem5::GPUStaticInst::_opcode, gem5::GPUStaticInst::disassembly, extData, instData, gem5::VegaISA::opSelectorToRegSym(), and gem5::VegaISA::REG_SRC_LITERAL.

hasSecondDword()

bool gem5::VegaISA::Inst_SOP1::hasSecondDword ( InFmt_SOP1 * iFmt )

private

Definition at line 285 of file op_encodings.cc.

References gem5::VegaISA::REG_SRC_LITERAL, and gem5::VegaISA::InFmt_SOP1::SSRC0.

Referenced by Inst_SOP1().

initOperandInfo()

void gem5::VegaISA::Inst_SOP1::initOperandInfo ( )

overridevirtual

Implements gem5::GPUStaticInst.

Definition at line 245 of file op_encodings.cc.

References gem5::GPUStaticInst::dstOps, gem5::VegaISA::VEGAGPUStaticInst::getOperandSize(), instData, gem5::VegaISA::isScalarReg(), gem5::GPUStaticInst::numDstRegOperands(), gem5::GPUStaticInst::numSrcRegOperands(), gem5::X86ISA::reg, and gem5::GPUStaticInst::srcOps.

instSize()

int gem5::VegaISA::Inst_SOP1::instSize ( ) const

overridevirtual

Implements gem5::GPUStaticInst.

Definition at line 279 of file op_encodings.cc.

References varSize.

Member Data Documentation

extData

InstFormat gem5::VegaISA::Inst_SOP1::extData

protected

Definition at line 132 of file op_encodings.hh.

Referenced by generateDisassembly(), and Inst_SOP1().

instData

InFmt_SOP1 gem5::VegaISA::Inst_SOP1::instData

protected

Definition at line 130 of file op_encodings.hh.

Referenced by gem5::VegaISA::Inst_SOP1__S_ABS_I32::execute(), gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64::execute(), gem5::VegaISA::Inst_SOP1__S_GETPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B32::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B64::execute(), gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SETPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8::execute(), gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B32::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64::execute(), generateDisassembly(), initOperandInfo(), and Inst_SOP1().

varSize

uint32_t gem5::VegaISA::Inst_SOP1::varSize

protected

Definition at line 133 of file op_encodings.hh.

Referenced by Inst_SOP1(), and instSize().

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The documentation for this class was generated from the following files:

• arch/amdgpu/vega/insts/op_encodings.hh
• arch/amdgpu/vega/insts/op_encodings.cc