gem5 v25.0.0.1
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compressed.hh File Reference
#include <string>
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"

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Classes

class  gem5::RiscvISA::CompRegOp
 Base class for compressed operations that work only on registers. More...

Namespaces

namespace  gem5
 Copyright (c) 2024 Arm Limited All rights reserved.
namespace  gem5::RiscvISA

Generated on Sat Oct 18 2025 08:06:47 for gem5 by doxygen 1.14.0