gem5
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cpu
capstone.hh
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/*
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* Copyright (c) 2023 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_CAPSTONE_HH__
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#define __CPU_CAPSTONE_HH__
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#include <capstone/capstone.h>
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#include "params/CapstoneDisassembler.hh"
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#include "
sim/insttracer.hh
"
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namespace
gem5
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{
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class
ThreadContext
;
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namespace
trace
{
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class
CapstoneDisassembler
:
public
InstDisassembler
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{
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public
:
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PARAMS
(
CapstoneDisassembler
);
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CapstoneDisassembler
(
const
Params
&
p
);
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std::string
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disassemble
(
StaticInstPtr
inst,
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const
PCStateBase
&
pc
,
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const
loader::SymbolTable
*symtab)
const override
;
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protected
:
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virtual
const
csh*
currHandle
(
const
PCStateBase
&
pc
)
const
= 0;
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};
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}
// namespace trace
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}
// namespace gem5
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#endif
// __CPU_CAPSTONE_HH__
gem5::PCStateBase
Definition
pcstate.hh:59
gem5::SimObject::Params
SimObjectParams Params
Definition
sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
thread_context.hh:89
gem5::loader::SymbolTable
Definition
symtab.hh:152
gem5::trace::CapstoneDisassembler::disassemble
std::string disassemble(StaticInstPtr inst, const PCStateBase &pc, const loader::SymbolTable *symtab) const override
Definition
capstone.cc:49
gem5::trace::CapstoneDisassembler::CapstoneDisassembler
CapstoneDisassembler(const Params &p)
Definition
capstone.cc:84
gem5::trace::CapstoneDisassembler::PARAMS
PARAMS(CapstoneDisassembler)
gem5::trace::CapstoneDisassembler::currHandle
virtual const csh * currHandle(const PCStateBase &pc) const =0
Return a pointer to the current capstone handle (csh).
gem5::trace::InstDisassembler::InstDisassembler
InstDisassembler(const SimObjectParams ¶ms)
Definition
insttracer.hh:325
insttracer.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition
pra_constants.hh:243
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5::trace
Definition
nativetrace.cc:58
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
gem5::StaticInstPtr
RefCountingPtr< StaticInst > StaticInstPtr
Definition
static_inst_fwd.hh:38
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