Namespaces
namespace	float_reg
namespace	int_reg
namespace	misc_reg

Classes
class	AddressErrorFault
class	AddressFault
class	BreakpointFault
class	CoprocessorUnusableFault
struct	CoreSpecific
class	Decoder
class	DspStateDisabledFault
class	EmuLinux
class	IntegerOverflowFault
class	InterruptFault
class	Interrupts
class	ISA
class	MachineCheckFault
class	MipsFault
class	MipsFaultBase
class	MMU
class	NonMaskableInterrupt
struct	PTE
class	RemoteGDB
class	ReservedInstructionFault
class	ResetFault
class	SEWorkload
class	SoftResetFault
class	StackTrace
class	SystemCallFault
class	ThreadFault
class	TLB
struct	TlbEntry
class	TlbFault
class	TlbInvalidFault
class	TlbModifiedFault
class	TlbRefillFault
class	TrapFault

Typedefs
typedef MipsFaultBase::FaultVals	FaultVals
typedef Addr	FaultVect
typedef GenericISA::DelaySlotPCState< 4 >	PCState
typedef uint32_t	MachInst
typedef uint64_t	ExtMachInst

Enumerations
enum	{ SIMD_FMT_L , SIMD_FMT_W , SIMD_FMT_PH , SIMD_FMT_QB , SIMD_NUM_FMTS }
enum	{ DSP_POS , DSP_SCOUNT , DSP_C , DSP_OUFLAG , DSP_CCOND , DSP_EFI , DSP_NUM_FIELDS }
enum	{ CMP_EQ , CMP_LT , CMP_LE }
enum	{ MODE_L , MODE_R , MODE_LA , MODE_RA , MODE_X }
enum	{ UNSIGNED , SIGNED }
enum	{ NOSATURATE , SATURATE }
enum	{ NOROUND , ROUND }
enum	ExcCode { ExcCodeDummy = 0 , ExcCodeInt = 0 , ExcCodeMod = 1 , ExcCodeTlbL = 2 , ExcCodeTlbS = 3 , ExcCodeAdEL = 4 , ExcCodeAdES = 5 , ExcCodeIBE = 6 , ExcCodeDBE = 7 , ExcCodeSys = 8 , ExcCodeBp = 9 , ExcCodeRI = 10 , ExcCodeCpU = 11 , ExcCodeOv = 12 , ExcCodeTr = 13 , ExcCodeC2E = 18 , ExcCodeMDMX = 22 , ExcCodeWatch = 23 , ExcCodeMCheck = 24 , ExcCodeThread = 25 , ExcCodeCacheErr = 30 }
enum	InterruptLevels { INTLEVEL_SOFTWARE_MIN = 4 , INTLEVEL_SOFTWARE_MAX = 19 , INTLEVEL_EXTERNAL_MIN = 20 , INTLEVEL_EXTERNAL_MAX = 34 , INTLEVEL_IRQ0 = 20 , INTLEVEL_IRQ1 = 21 , INTINDEX_ETHERNET = 0 , INTINDEX_SCSI = 1 , INTLEVEL_IRQ2 = 22 , INTLEVEL_IRQ3 = 23 , INTLEVEL_SERIAL = 33 , NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }
enum	FCSRBits { Inexact = 1 , Underflow , Overflow , DivideByZero , Invalid , Unimplemented }
enum	FCSRFields { Flag_Field = 1 , Enable_Field = 6 , Cause_Field = 11 }
enum	ConvertType { SINGLE_TO_DOUBLE , SINGLE_TO_WORD , SINGLE_TO_LONG , DOUBLE_TO_SINGLE , DOUBLE_TO_WORD , DOUBLE_TO_LONG , LONG_TO_SINGLE , LONG_TO_DOUBLE , LONG_TO_WORD , LONG_TO_PS , WORD_TO_SINGLE , WORD_TO_DOUBLE , WORD_TO_LONG , WORD_TO_PS , PL_TO_SINGLE , PU_TO_SINGLE }
enum	RoundMode { RND_ZERO , RND_DOWN , RND_UP , RND_NEAREST }

Functions
int32_t	bitrev (int32_t value)
uint64_t	dspSaturate (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
uint64_t	checkOverflow (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
uint64_t	signExtend (uint64_t value, int32_t signpos)
uint64_t	addHalfLsb (uint64_t value, int32_t lsbpos)
int32_t	dspAbs (int32_t a, int32_t fmt, uint32_t *dspctl)
int32_t	dspAdd (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
int32_t	dspAddh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
int32_t	dspSub (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
int32_t	dspSubh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
int32_t	dspShll (int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
int32_t	dspShrl (int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
int32_t	dspShra (int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
int32_t	dspMul (int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
int32_t	dspMulq (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
int32_t	dspMuleu (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
int32_t	dspMuleq (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
int64_t	dspDpaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
int64_t	dspDpsq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
int64_t	dspDpa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
int64_t	dspDps (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
int64_t	dspMaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
int64_t	dspMulsa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
int64_t	dspMulsaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
void	dspCmp (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
int32_t	dspCmpg (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
int32_t	dspCmpgd (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
int32_t	dspPrece (int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
int32_t	dspPrecrqu (int32_t a, int32_t b, uint32_t *dspctl)
int32_t	dspPrecrq (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
int32_t	dspPrecrSra (int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
int32_t	dspPick (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
int32_t	dspPack (int32_t a, int32_t b, int32_t fmt)
int32_t	dspExtr (int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
int32_t	dspExtp (int64_t dspac, int32_t size, uint32_t *dspctl)
int32_t	dspExtpd (int64_t dspac, int32_t size, uint32_t *dspctl)
void	simdPack (uint64_t values_ptr, int32_t reg, int32_t fmt)
void	simdUnpack (int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
void	writeDSPControl (uint32_t *dspctl, uint32_t value, uint32_t mask)
uint32_t	readDSPControl (uint32_t *dspctl, uint32_t mask)
	BitUnion32 (DebugReg) Bitfield< 31 > dbd
	SubBitUnion (ejtagVer, 17, 15) Bitfield< 17 > ejtagVer2
	EndSubBitUnion (ejtagVer) Bitfield< 14
	EndBitUnion (DebugReg) BitUnion32(TraceControlReg) Bitfield< 31 > ts
	EndBitUnion (TraceControlReg) BitUnion32(TraceControl2Reg) Bitfield< 29 > cpuidv
	EndBitUnion (TraceControl2Reg) BitUnion32(TraceBPCReg) Bitfield< 31 > mb
	EndBitUnion (TraceBPCReg) BitUnion32(TraceBPC2Reg) Bitfield< 17
	EndBitUnion (TraceBPC2Reg) BitUnion32(Debug2Reg) Bitfield< 3 > prm
static uint8_t	getCauseIP (ThreadContext *tc)
static void	setCauseIP (ThreadContext *tc, uint8_t val)
static SyscallReturn	unameFunc (SyscallDesc desc, ThreadContext tc, VPtr< Linux::utsname > name)
	Target uname() handler.
static SyscallReturn	sys_getsysinfoFunc (SyscallDesc desc, ThreadContext tc, unsigned op, unsigned bufPtr, unsigned nbytes)
	Target sys_getsysyinfo() handler.
static SyscallReturn	sys_setsysinfoFunc (SyscallDesc desc, ThreadContext tc, unsigned op, VPtr<> bufPtr, unsigned nbytes)
	Target sys_setsysinfo() handler.
static SyscallReturn	setThreadAreaFunc (SyscallDesc desc, ThreadContext tc, VPtr<> addr)
static RegVal	readRegOtherThread (ThreadContext *tc, const RegId &reg, ThreadID tid=InvalidThreadID)
static void	setRegOtherThread (ThreadContext *tc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
static RegVal	readRegOtherThread (ExecContext *xc, const RegId &reg, ThreadID tid=InvalidThreadID)
static void	setRegOtherThread (ExecContext *xc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
template<class TC>
unsigned	getVirtProcNum (TC *tc)
template<class TC>
unsigned	getTargetThread (TC *tc)
template<class TC>
void	haltThread (TC *tc)
template<class TC>
void	restoreThread (TC *tc)
template<class TC>
void	forkThread (TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
template<class TC>
int	yieldThread (TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
template<class TC>
void	updateStatusView (TC *tc)
template<class TC>
void	updateTCStatusView (TC *tc)
	BitUnion32 (MVPControlReg) Bitfield< 3 > cpa
	EndBitUnion (MVPControlReg) BitUnion32(MVPConf0Reg) Bitfield< 31 > m
	EndBitUnion (MVPConf0Reg) BitUnion32(VPEControlReg) Bitfield< 21 > ysi
	EndBitUnion (VPEControlReg) BitUnion32(VPEConf0Reg) Bitfield< 31 > m
	EndBitUnion (VPEConf0Reg) BitUnion32(TCBindReg) Bitfield< 28
	EndBitUnion (TCBindReg) BitUnion32(TCStatusReg) Bitfield< 31
	EndBitUnion (TCStatusReg) BitUnion32(TCHaltReg) Bitfield< 0 > h
	BitUnion32 (IndexReg) Bitfield< 31 > p
	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
	EndSubBitUnion (cu) Bitfield< 27 > rp
	SubBitUnion (im, 15, 8) Bitfield< 15 > im7
	EndSubBitUnion (im) Bitfield< 7 > kx
	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
	EndSubBitUnion (ip)
	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
constexpr RegClass	floatRegClass (FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
constexpr RegClass	intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
constexpr RegClass	miscRegClass (MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
uint64_t	fpConvert (ConvertType cvt_type, double fp_val)
double	roundFP (double val, int digits)
double	truncFP (double val)
bool	getCondCode (uint32_t fcsr, int cc_idx)
uint32_t	genCCVector (uint32_t fcsr, int cc_num, uint32_t cc_val)
uint32_t	genInvalidVector (uint32_t fcsr_bits)
bool	isNan (void *val_ptr, int size)
bool	isQnan (void *val_ptr, int size)
bool	isSnan (void *val_ptr, int size)
Addr	TruncPage (Addr addr)
Addr	RoundPage (Addr addr)

Variables
const uint32_t	DSP_CTL_POS [DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }
const uint32_t	DSP_CTL_MASK [DSP_NUM_FIELDS]
const uint32_t	SIMD_MAX_VALS = 4
const uint32_t	SIMD_NVALS [SIMD_NUM_FMTS] = { 1, 1, 2, 4 }
const uint32_t	SIMD_NBITS [SIMD_NUM_FMTS] = { 64, 32, 16, 8 }
const uint32_t	SIMD_LOG2N [SIMD_NUM_FMTS] = { 6, 5, 4, 3 }
const uint64_t	FIXED_L_SMAX = 0x7fffffffffffffffULL
const uint64_t	FIXED_W_SMAX = 0x000000007fffffffULL
const uint64_t	FIXED_H_SMAX = 0x0000000000007fffULL
const uint64_t	FIXED_B_SMAX = 0x000000000000007fULL
const uint64_t	FIXED_L_UMAX = 0xffffffffffffffffULL
const uint64_t	FIXED_W_UMAX = 0x00000000ffffffffULL
const uint64_t	FIXED_H_UMAX = 0x000000000000ffffULL
const uint64_t	FIXED_B_UMAX = 0x00000000000000ffULL
const uint64_t	FIXED_SMAX [SIMD_NUM_FMTS]
const uint64_t	FIXED_UMAX [SIMD_NUM_FMTS]
const uint64_t	FIXED_L_SMIN = 0x8000000000000000ULL
const uint64_t	FIXED_W_SMIN = 0xffffffff80000000ULL
const uint64_t	FIXED_H_SMIN = 0xffffffffffff8000ULL
const uint64_t	FIXED_B_SMIN = 0xffffffffffffff80ULL
const uint64_t	FIXED_L_UMIN = 0x0000000000000000ULL
const uint64_t	FIXED_W_UMIN = 0x0000000000000000ULL
const uint64_t	FIXED_H_UMIN = 0x0000000000000000ULL
const uint64_t	FIXED_B_UMIN = 0x0000000000000000ULL
const uint64_t	FIXED_SMIN [SIMD_NUM_FMTS]
const uint64_t	FIXED_UMIN [SIMD_NUM_FMTS]
Bitfield< 30 >	dm
Bitfield< 29 >	nodcr
Bitfield< 28 >	lsnm
Bitfield< 27 >	doze
Bitfield< 26 >	halt
Bitfield< 25 >	conutdm
Bitfield< 24 >	ibusep
Bitfield< 23 >	mcheckep
Bitfield< 22 >	cacheep
Bitfield< 21 >	dbusep
Bitfield< 20, 19 >	iexi
Bitfield< 19 >	ddbsImpr
Bitfield< 18 >	ddblImpr
Bitfield< 16 >	ejtagVer1
Bitfield< 15 >	ejtagVer0
	dexcCode
Bitfield< 9 >	nosst
Bitfield< 8 >	sst
Bitfield< 7 >	offline
Bitfield< 6 >	dibimpr
Bitfield< 5 >	dint
Bitfield< 4 >	dib
Bitfield< 3 >	ddbs
Bitfield< 2 >	ddbl
Bitfield< 1 >	dbp
Bitfield< 0 >	dss
Bitfield< 30 >	ut
Bitfield< 27 >	tb
Bitfield< 26 >	io
Bitfield< 25 >	d
Bitfield< 24 >	e
Bitfield< 23 >	k
Bitfield< 22 >	s
Bitfield< 21 >	u
Bitfield< 20, 13 >	asidM
Bitfield< 12, 5 >	asid
Bitfield< 4 >	g
Bitfield< 3 >	tfcr
Bitfield< 2 >	tlsm
Bitfield< 1 >	tim
Bitfield< 0 >	on
Bitfield< 28, 21 >	cpuid
Bitfield< 20 >	tcv
Bitfield< 19, 12 >	tcnum
Bitfield< 11, 7 >	mode
Bitfield< 6, 5 >	validModes
Bitfield< 4 >	tbi
Bitfield< 3 >	tbu
Bitfield< 2, 0 >	syp
Bitfield< 27 >	ate
Bitfield< 26, 24 >	bpc8
Bitfield< 23, 21 >	bpc7
Bitfield< 20, 18 >	bpc6
Bitfield< 17, 15 >	bpc5
Bitfield< 14, 12 >	bpc4
Bitfield< 11, 9 >	bpc3
Bitfield< 8, 6 >	bpc2
Bitfield< 5, 3 >	bpc1
Bitfield< 2, 0 >	bpc0
	bpc14
Bitfield< 14, 12 >	bpc13
Bitfield< 11, 9 >	bpc12
Bitfield< 8, 6 >	bpc11
Bitfield< 5, 3 >	bpc10
Bitfield< 2, 0 >	bpc9
Bitfield< 2 >	dq
Bitfield< 1 >	tup
Bitfield< 0 >	paco
template<>
FaultVals	MipsFault< SystemCallFault >::vals
template<>
FaultVals	MipsFault< ReservedInstructionFault >::vals
template<>
FaultVals	MipsFault< ThreadFault >::vals
template<>
FaultVals	MipsFault< IntegerOverflowFault >::vals
template<>
FaultVals	MipsFault< TrapFault >::vals
template<>
FaultVals	MipsFault< BreakpointFault >::vals
template<>
FaultVals	MipsFault< DspStateDisabledFault >::vals
template<>
FaultVals	MipsFault< MachineCheckFault >::vals
template<>
FaultVals	MipsFault< ResetFault >::vals
template<>
FaultVals	MipsFault< SoftResetFault >::vals
template<>
FaultVals	MipsFault< NonMaskableInterrupt >::vals
template<>
FaultVals	MipsFault< CoprocessorUnusableFault >::vals
template<>
FaultVals	MipsFault< InterruptFault >::vals
template<>
FaultVals	MipsFault< AddressErrorFault >::vals
template<>
FaultVals	MipsFault< TlbInvalidFault >::vals
template<>
FaultVals	MipsFault< TlbRefillFault >::vals
template<>
MipsFaultBase::FaultVals	MipsFault< TlbModifiedFault >::vals
Bitfield< 2 >	stlb
Bitfield< 1 >	vpc
Bitfield< 0 >	evp
Bitfield< 29 >	tlbs
Bitfield< 28 >	gs
Bitfield< 27 >	pcp
Bitfield< 25, 16 >	ptlbe
Bitfield< 15 >	tca
Bitfield< 13, 10 >	pvpe
Bitfield< 7, 0 >	ptc
Bitfield< 18, 16 >	excpt
Bitfield< 15 >	te
Bitfield< 7, 0 >	targTC
Bitfield< 28, 21 >	xtc
Bitfield< 19 >	tcs
Bitfield< 18 >	scs
Bitfield< 17 >	dcs
Bitfield< 16 >	ics
Bitfield< 1 >	mvp
Bitfield< 0 >	vpa
	curTC
Bitfield< 20, 18 >	a0
Bitfield< 17 >	tbe
Bitfield< 3, 0 >	curVPE
	tcu
Bitfield< 27 >	tmx
Bitfield< 24, 23 >	rnst
Bitfield< 21 >	tds
Bitfield< 20 >	dt
Bitfield< 19, 16 >	impl
Bitfield< 15 >	da
Bitfield< 13 >	a
Bitfield< 12, 11 >	tksu
Bitfield< 10 >	ixmt
const Addr	PageShift = 13
const Addr	PageBytes = 1ULL << PageShift
Bitfield< 30, 0 >	index
	random
	fill
Bitfield< 29, 6 >	pfn
Bitfield< 5, 3 >	c
Bitfield< 1 >	v
	pteBase
Bitfield< 22, 4 >	badVPN2
	mask
Bitfield< 12, 11 >	maskx
	aseUp
Bitfield< 29 >	elpa
Bitfield< 28 >	esp
Bitfield< 12, 8 >	aseDn
	wired
	r
Bitfield< 39, 13 >	vpn2
Bitfield< 12, 11 >	vpn2x
Bitfield< 31 >	cu3
Bitfield< 30 >	cu2
Bitfield< 29 >	cu1
Bitfield< 28 >	cu0
Bitfield< 26 >	fr
Bitfield< 25 >	re
Bitfield< 24 >	mx
Bitfield< 23 >	px
Bitfield< 22 >	bev
Bitfield< 21 >	ts
Bitfield< 20 >	sr
Bitfield< 19 >	nmi
Bitfield< 15, 10 >	ipl
Bitfield< 14 >	im6
Bitfield< 13 >	im5
Bitfield< 12 >	im4
Bitfield< 11 >	im3
Bitfield< 10 >	im2
Bitfield< 9 >	im1
Bitfield< 8 >	im0
Bitfield< 6 >	sx
Bitfield< 5 >	ux
Bitfield< 4, 3 >	ksu
Bitfield< 4 >	um
Bitfield< 3 >	r0
Bitfield< 2 >	erl
Bitfield< 1 >	exl
Bitfield< 0 >	ie
	ipti
Bitfield< 28, 26 >	ippci
Bitfield< 9, 5 >	vs
	hss
Bitfield< 21, 18 >	eicss
Bitfield< 15, 12 >	ess
Bitfield< 9, 6 >	pss
Bitfield< 3, 0 >	css
	ssv7
Bitfield< 27, 24 >	ssv6
Bitfield< 23, 20 >	ssv5
Bitfield< 19, 16 >	ssv4
Bitfield< 15, 12 >	ssv3
Bitfield< 11, 8 >	ssv2
Bitfield< 7, 4 >	ssv1
Bitfield< 3, 0 >	ssv0
Bitfield< 30 >	ti
Bitfield< 29, 28 >	ce
Bitfield< 27 >	dc
Bitfield< 26 >	pci
Bitfield< 23 >	iv
Bitfield< 22 >	wp
Bitfield< 15, 10 >	ripl
Bitfield< 14 >	ip6
Bitfield< 13 >	ip5
Bitfield< 12 >	ip4
Bitfield< 11 >	ip3
Bitfield< 10 >	ip2
Bitfield< 9 >	ip1
Bitfield< 8 >	ip0
Bitfield< 6, 2 >	excCode
	coOp
Bitfield< 23, 16 >	coId
Bitfield< 15, 8 >	procId
Bitfield< 7, 0 >	rev
	exceptionBase
Bitfield< 9, 9 >	cpuNum
Bitfield< 30, 28 >	k23
Bitfield< 27, 25 >	ku
Bitfield< 15 >	be
Bitfield< 14, 13 >	at
Bitfield< 12, 10 >	ar
Bitfield< 9, 7 >	mt
Bitfield< 3 >	vi
Bitfield< 2, 0 >	k0
Bitfield< 30, 25 >	mmuSize
Bitfield< 24, 22 >	is
Bitfield< 21, 19 >	il
Bitfield< 18, 16 >	ia
Bitfield< 15, 13 >	ds
Bitfield< 12, 10 >	dl
Bitfield< 6 >	c2
Bitfield< 5 >	md
Bitfield< 4 >	pc
Bitfield< 3 >	wr
Bitfield< 2 >	ca
Bitfield< 1 >	ep
Bitfield< 0 >	fp
Bitfield< 30, 28 >	tu
Bitfield< 23, 20 >	tl
Bitfield< 19, 16 >	ta
Bitfield< 15, 12 >	su
Bitfield< 11, 8 >	ss
Bitfield< 7, 4 >	sl
Bitfield< 3, 0 >	sa
Bitfield< 10 >	dspp
Bitfield< 7 >	lpa
Bitfield< 6 >	veic
Bitfield< 5 >	vint
Bitfield< 4 >	sp
Bitfield< 1 >	sm
	vaddr
Bitfield< 2 >	i
Bitfield< 0 >	w
Bitfield< 10, 5 >	event
Bitfield< 30 >	ec
Bitfield< 29 >	ed
Bitfield< 28 >	et
Bitfield< 27 >	es
Bitfield< 26 >	ee
Bitfield< 25 >	eb
	pTagLo
Bitfield< 7, 6 >	pState
Bitfield< 5 >	l
Bitfield< 0 >	p
const uint32_t	MIPS32_QNAN = 0x7fbfffff
const uint64_t	MIPS64_QNAN = 0x7ff7ffffffffffffULL
const int	MaxShadowRegSets = 16

Typedef Documentation

◆ ExtMachInst

typedef uint64_t gem5::MipsISA::ExtMachInst

Definition at line 43 of file types.hh.

◆ FaultVals

typedef MipsFaultBase::FaultVals gem5::MipsISA::FaultVals

Definition at line 46 of file faults.cc.

◆ FaultVect

typedef Addr gem5::MipsISA::FaultVect

Definition at line 47 of file faults.hh.

◆ MachInst

typedef uint32_t gem5::MipsISA::MachInst

Definition at line 42 of file types.hh.

◆ PCState

typedef GenericISA::DelaySlotPCState<4> gem5::MipsISA::PCState

Definition at line 40 of file pcstate.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
CMP_EQ
CMP_LT
CMP_LE

Definition at line 66 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
NOSATURATE
SATURATE

Definition at line 85 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
UNSIGNED
SIGNED

Definition at line 84 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
NOROUND
ROUND

Definition at line 86 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
MODE_L
MODE_R
MODE_LA
MODE_RA
MODE_X

Definition at line 74 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
DSP_POS
DSP_SCOUNT
DSP_C
DSP_OUFLAG
DSP_CCOND
DSP_EFI
DSP_NUM_FIELDS

Definition at line 54 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
SIMD_FMT_L
SIMD_FMT_W
SIMD_FMT_PH
SIMD_FMT_QB
SIMD_NUM_FMTS

Definition at line 44 of file dsp.hh.

◆ ConvertType

enum gem5::MipsISA::ConvertType

Enumerator
SINGLE_TO_DOUBLE
SINGLE_TO_WORD
SINGLE_TO_LONG
DOUBLE_TO_SINGLE
DOUBLE_TO_WORD
DOUBLE_TO_LONG
LONG_TO_SINGLE
LONG_TO_DOUBLE
LONG_TO_WORD
LONG_TO_PS
WORD_TO_SINGLE
WORD_TO_DOUBLE
WORD_TO_LONG
WORD_TO_PS
PL_TO_SINGLE
PU_TO_SINGLE

Definition at line 46 of file types.hh.

◆ ExcCode

enum gem5::MipsISA::ExcCode

Enumerator
ExcCodeDummy
ExcCodeInt
ExcCodeMod
ExcCodeTlbL
ExcCodeTlbS
ExcCodeAdEL
ExcCodeAdES
ExcCodeIBE
ExcCodeDBE
ExcCodeSys
ExcCodeBp
ExcCodeRI
ExcCodeCpU
ExcCodeOv
ExcCodeTr
ExcCodeC2E
ExcCodeMDMX
ExcCodeWatch
ExcCodeMCheck
ExcCodeThread
ExcCodeCacheErr

Definition at line 49 of file faults.hh.

◆ FCSRBits

enum gem5::MipsISA::FCSRBits

Enumerator
Inexact
Underflow
Overflow
DivideByZero
Invalid
Unimplemented

Definition at line 140 of file float.hh.

◆ FCSRFields

enum gem5::MipsISA::FCSRFields

Enumerator
Flag_Field
Enable_Field
Cause_Field

Definition at line 150 of file float.hh.

◆ InterruptLevels

enum gem5::MipsISA::InterruptLevels

Enumerator
INTLEVEL_SOFTWARE_MIN
INTLEVEL_SOFTWARE_MAX
INTLEVEL_EXTERNAL_MIN
INTLEVEL_EXTERNAL_MAX
INTLEVEL_IRQ0
INTLEVEL_IRQ1
INTINDEX_ETHERNET
INTINDEX_SCSI
INTLEVEL_IRQ2
INTLEVEL_IRQ3
INTLEVEL_SERIAL
NumInterruptLevels

Definition at line 43 of file interrupts.cc.

◆ RoundMode

enum gem5::MipsISA::RoundMode

Enumerator
RND_ZERO
RND_DOWN
RND_UP
RND_NEAREST

Definition at line 71 of file types.hh.

Function Documentation

◆ addHalfLsb()

uint64_t gem5::MipsISA::addHalfLsb	(	uint64_t	value,
		int32_t	lsbpos )

Definition at line 128 of file dsp.cc.

Referenced by dspAddh(), dspExtr(), dspMulq(), dspPrecrq(), dspPrecrSra(), dspShra(), and dspSubh().

◆ bitrev()

int32_t gem5::MipsISA::bitrev ( int32_t value )

Definition at line 42 of file dsp.cc.

References i, and gem5::ArmISA::shift.

◆ BitUnion32() [1/3]

gem5::MipsISA::BitUnion32 ( DebugReg )

◆ BitUnion32() [2/3]

gem5::MipsISA::BitUnion32 ( IndexReg )

References p.

◆ BitUnion32() [3/3]

gem5::MipsISA::BitUnion32 ( MVPControlReg )

◆ checkOverflow()

uint64_t gem5::MipsISA::checkOverflow	(	uint64_t	value,
		int32_t	fmt,
		int32_t	sign,
		uint32_t *	overflow )

Definition at line 90 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspExtr(), dspMul(), dspShll(), and dspSub().

◆ dspAbs()

int32_t gem5::MipsISA::dspAbs	(	int32_t	a,
		int32_t	fmt,
		uint32_t *	dspctl )

Definition at line 134 of file dsp.cc.

References a, DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAdd()

int32_t gem5::MipsISA::dspAdd	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl )

Definition at line 165 of file dsp.cc.

References a, gem5::ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAddh()

int32_t gem5::MipsISA::dspAddh	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign )

Definition at line 197 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspCmp()

void gem5::MipsISA::dspCmp	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op,
		uint32_t *	dspctl )

Definition at line 770 of file dsp.cc.

References a, gem5::ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, gem5::X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspCmpg()

int32_t gem5::MipsISA::dspCmpg	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op )

Definition at line 803 of file dsp.cc.

References a, gem5::ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, i, gem5::X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspCmpgd()

int32_t gem5::MipsISA::dspCmpgd	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op,
		uint32_t *	dspctl )

Definition at line 835 of file dsp.cc.

References a, gem5::ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, gem5::X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspDpa()

int64_t gem5::MipsISA::dspDpa	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	sign,
		int32_t	mode )

Definition at line 627 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpaq()

int64_t gem5::MipsISA::dspDpaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	infmt,
		int32_t	outfmt,
		int32_t	postsat,
		int32_t	mode,
		uint32_t *	dspctl )

Definition at line 493 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, gem5::bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, gem5::insertBits(), mode, MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDps()

int64_t gem5::MipsISA::dspDps	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	sign,
		int32_t	mode )

Definition at line 655 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpsq()

int64_t gem5::MipsISA::dspDpsq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	infmt,
		int32_t	outfmt,
		int32_t	postsat,
		int32_t	mode,
		uint32_t *	dspctl )

Definition at line 560 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, gem5::bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, gem5::insertBits(), mode, MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspExtp()

int32_t gem5::MipsISA::dspExtp	(	int64_t	dspac,
		int32_t	size,
		uint32_t *	dspctl )

Definition at line 1083 of file dsp.cc.

References gem5::bits(), and gem5::insertBits().

◆ dspExtpd()

int32_t gem5::MipsISA::dspExtpd	(	int64_t	dspac,
		int32_t	size,
		uint32_t *	dspctl )

Definition at line 1103 of file dsp.cc.

References gem5::bits(), and gem5::insertBits().

◆ dspExtr()

int32_t gem5::MipsISA::dspExtr	(	int64_t	dspac,
		int32_t	fmt,
		int32_t	sa,
		int32_t	round,
		int32_t	saturate,
		uint32_t *	dspctl )

Definition at line 1040 of file dsp.cc.

References addHalfLsb(), gem5::bits(), checkOverflow(), dspSaturate(), FIXED_SMAX, gem5::insertBits(), sa, SIGNED, and SIMD_FMT_L.

◆ dspMaq()

int64_t gem5::MipsISA::dspMaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	mode,
		int32_t	saturate,
		uint32_t *	dspctl )

Definition at line 683 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, gem5::insertBits(), mode, MODE_L, MODE_R, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspMul()

int32_t gem5::MipsISA::dspMul	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		uint32_t *	dspctl )

Definition at line 390 of file dsp.cc.

References a, gem5::ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleq()

int32_t gem5::MipsISA::dspMuleq	(	int32_t	a,
		int32_t	b,
		int32_t	mode,
		uint32_t *	dspctl )

Definition at line 456 of file dsp.cc.

References a, gem5::ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, mode, MODE_L, MODE_R, SIGNED, SIMD_FMT_PH, SIMD_FMT_W, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleu()

int32_t gem5::MipsISA::dspMuleu	(	int32_t	a,
		int32_t	b,
		int32_t	mode,
		uint32_t *	dspctl )

Definition at line 422 of file dsp.cc.

References a, gem5::ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, mode, MODE_L, MODE_R, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), UNSIGNED, and writeDSPControl().

◆ dspMulq()

int32_t gem5::MipsISA::dspMulq	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	round,
		uint32_t *	dspctl )

Definition at line 349 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMulsa()

int64_t gem5::MipsISA::dspMulsa	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt )

Definition at line 727 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, SIGNED, SIMD_MAX_VALS, and simdUnpack().

◆ dspMulsaq()

int64_t gem5::MipsISA::dspMulsaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		uint32_t *	dspctl )

Definition at line 741 of file dsp.cc.

References a, gem5::X86ISA::ac, gem5::ArmISA::b, FIXED_SMAX, FIXED_SMIN, i, gem5::insertBits(), SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspPack()

int32_t gem5::MipsISA::dspPack	(	int32_t	a,
		int32_t	b,
		int32_t	fmt )

Definition at line 1021 of file dsp.cc.

References a, gem5::ArmISA::b, SIMD_MAX_VALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPick()

int32_t gem5::MipsISA::dspPick	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		uint32_t *	dspctl )

Definition at line 996 of file dsp.cc.

References a, gem5::ArmISA::b, gem5::bits(), DSP_CCOND, DSP_CTL_POS, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrece()

int32_t gem5::MipsISA::dspPrece	(	int32_t	a,
		int32_t	infmt,
		int32_t	insign,
		int32_t	outfmt,
		int32_t	outsign,
		int32_t	mode )

Definition at line 872 of file dsp.cc.

References a, i, mode, MODE_L, MODE_LA, MODE_R, MODE_RA, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrq()

int32_t gem5::MipsISA::dspPrecrq	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		uint32_t *	dspctl )

Definition at line 943 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, dspSaturate(), gem5::insertBits(), SIGNED, SIMD_MAX_VALS, simdPack(), and simdUnpack().

◆ dspPrecrqu()

int32_t gem5::MipsISA::dspPrecrqu	(	int32_t	a,
		int32_t	b,
		uint32_t *	dspctl )

Definition at line 914 of file dsp.cc.

References a, gem5::ArmISA::b, dspSaturate(), i, gem5::insertBits(), SIGNED, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NBITS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrSra()

int32_t gem5::MipsISA::dspPrecrSra	(	int32_t	a,
		int32_t	b,
		int32_t	sa,
		int32_t	fmt,
		int32_t	round )

Definition at line 968 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspSaturate()

uint64_t gem5::MipsISA::dspSaturate	(	uint64_t	value,
		int32_t	fmt,
		int32_t	sign,
		uint32_t *	overflow )

Definition at line 60 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspDpaq(), dspDpsq(), dspExtr(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspPrecrq(), dspPrecrqu(), dspShll(), and dspSub().

◆ dspShll()

int32_t gem5::MipsISA::dspShll	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl )

Definition at line 277 of file dsp.cc.

References a, gem5::bits(), checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, sa, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspShra()

int32_t gem5::MipsISA::dspShra	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign,
		uint32_t *	dspctl )

Definition at line 325 of file dsp.cc.

References a, addHalfLsb(), gem5::bits(), i, sa, SIGNED, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspShrl()

int32_t gem5::MipsISA::dspShrl	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	sign )

Definition at line 306 of file dsp.cc.

References a, gem5::bits(), i, sa, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspSub()

int32_t gem5::MipsISA::dspSub	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl )

Definition at line 221 of file dsp.cc.

References a, gem5::ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspSubh()

int32_t gem5::MipsISA::dspSubh	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign )

Definition at line 252 of file dsp.cc.

References a, addHalfLsb(), gem5::ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ EndBitUnion() [1/35]

gem5::MipsISA::EndBitUnion ( CacheErrReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [2/35]

gem5::MipsISA::EndBitUnion ( CauseReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [3/35]

gem5::MipsISA::EndBitUnion ( Config1Reg )

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

◆ EndBitUnion() [4/35]

gem5::MipsISA::EndBitUnion ( Config2Reg )

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

◆ EndBitUnion() [5/35]

gem5::MipsISA::EndBitUnion ( Config3Reg )

References gem5::QARMA::BitUnion64(), and EndBitUnion().

◆ EndBitUnion() [6/35]

gem5::MipsISA::EndBitUnion ( ConfigReg )

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

◆ EndBitUnion() [7/35]

gem5::MipsISA::EndBitUnion ( ContextReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [8/35]

gem5::MipsISA::EndBitUnion ( DebugReg )

◆ EndBitUnion() [9/35]

gem5::MipsISA::EndBitUnion ( EBaseReg )

References BitUnion32(), EndBitUnion(), and gem5::ArmISA::m.

◆ EndBitUnion() [10/35]

gem5::MipsISA::EndBitUnion ( EntryHiReg )

References BitUnion32(), EndBitUnion(), and SubBitUnion().

◆ EndBitUnion() [11/35]

gem5::MipsISA::EndBitUnion ( EntryLoReg )

References gem5::QARMA::BitUnion64(), and EndBitUnion().

◆ EndBitUnion() [12/35]

gem5::MipsISA::EndBitUnion ( HWREnaReg )

References gem5::QARMA::BitUnion64(), and EndBitUnion().

◆ EndBitUnion() [13/35]

gem5::MipsISA::EndBitUnion ( IndexReg )

◆ EndBitUnion() [14/35]

gem5::MipsISA::EndBitUnion ( IntCtlReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [15/35]

gem5::MipsISA::EndBitUnion ( MVPConf0Reg )

◆ EndBitUnion() [16/35]

gem5::MipsISA::EndBitUnion ( MVPControlReg )

References gem5::ArmISA::m.

◆ EndBitUnion() [17/35]

gem5::MipsISA::EndBitUnion ( PageGrainReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [18/35]

gem5::MipsISA::EndBitUnion ( PageMaskReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [19/35]

gem5::MipsISA::EndBitUnion ( PerfCntCtlReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [20/35]

gem5::MipsISA::EndBitUnion ( PRIdReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [21/35]

gem5::MipsISA::EndBitUnion ( RandomReg )

References gem5::QARMA::BitUnion64(), and EndBitUnion().

◆ EndBitUnion() [22/35]

gem5::MipsISA::EndBitUnion ( SRSCtlReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [23/35]

gem5::MipsISA::EndBitUnion ( SRSMapReg )

References gem5::PowerISA::bd, BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [24/35]

gem5::MipsISA::EndBitUnion ( StatusReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [25/35]

gem5::MipsISA::EndBitUnion ( TCBindReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [26/35]

gem5::MipsISA::EndBitUnion ( TCStatusReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [27/35]

gem5::MipsISA::EndBitUnion ( TraceBPC2Reg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [28/35]

gem5::MipsISA::EndBitUnion ( TraceBPCReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [29/35]

gem5::MipsISA::EndBitUnion ( TraceControl2Reg )

References BitUnion32(), e, EndBitUnion(), and gem5::PowerISA::mb.

◆ EndBitUnion() [30/35]

gem5::MipsISA::EndBitUnion ( TraceControlReg )

References BitUnion32(), and EndBitUnion().

◆ EndBitUnion() [31/35]

gem5::MipsISA::EndBitUnion ( VPEConf0Reg )

◆ EndBitUnion() [32/35]

gem5::MipsISA::EndBitUnion ( VPEControlReg )

References gem5::ArmISA::m.

◆ EndBitUnion() [33/35]

gem5::MipsISA::EndBitUnion ( WatchHiReg )

References BitUnion32(), EndBitUnion(), gem5::ArmISA::m, and w.

◆ EndBitUnion() [34/35]

gem5::MipsISA::EndBitUnion ( WatchLoReg )

References asid, BitUnion32(), EndBitUnion(), g, i, gem5::ArmISA::m, mask, r, and w.

◆ EndBitUnion() [35/35]

gem5::MipsISA::EndBitUnion ( WiredReg )

References BitUnion32(), EndBitUnion(), impl, and mask.

◆ EndSubBitUnion() [1/4]

gem5::MipsISA::EndSubBitUnion ( cu )

References EndSubBitUnion().

◆ EndSubBitUnion() [2/4]

gem5::MipsISA::EndSubBitUnion ( ejtagVer )

References EndSubBitUnion().

Referenced by EndSubBitUnion(), EndSubBitUnion(), EndSubBitUnion(), and EndSubBitUnion().

◆ EndSubBitUnion() [3/4]

gem5::MipsISA::EndSubBitUnion ( im )

References EndSubBitUnion().

◆ EndSubBitUnion() [4/4]

gem5::MipsISA::EndSubBitUnion ( ip )

References EndSubBitUnion().

◆ floatRegClass()

RegClass gem5::MipsISA::floatRegClass	(	FloatRegClass	,
		FloatRegClassName	,
		float_reg::NumRegs	,
		debug::FloatRegs	)

inlineconstexpr

References gem5::FloatRegClass, gem5::FloatRegClassName, and gem5::MipsISA::float_reg::NumRegs.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::MipsISA::ISA::ISA(), and gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs().

◆ forkThread()

template<class TC>

void gem5::MipsISA::forkThread	(	TC *	tc,
		Fault &	fault,
		int	Rd_bits,
		int	Rs,
		int	Rt )

Definition at line 169 of file mt.hh.

References intRegClass(), miscRegClass(), gem5::MipsISA::misc_reg::MvpConf0, readRegOtherThread(), setRegOtherThread(), gem5::MipsISA::misc_reg::Status, gem5::ArmISA::status, gem5::MipsISA::misc_reg::TcBind, gem5::MipsISA::misc_reg::TcHalt, gem5::MipsISA::misc_reg::TcRestart, gem5::MipsISA::misc_reg::TcStatus, and gem5::MipsISA::misc_reg::VpeControl.

◆ fpConvert()

uint64_t gem5::MipsISA::fpConvert	(	ConvertType	cvt_type,
		double	fp_val )

Definition at line 50 of file utility.cc.

References panic, SINGLE_TO_DOUBLE, SINGLE_TO_WORD, WORD_TO_DOUBLE, and WORD_TO_SINGLE.

◆ genCCVector()

uint32_t gem5::MipsISA::genCCVector	(	uint32_t	fcsr,
		int	cc_num,
		uint32_t	cc_val )

Definition at line 120 of file utility.cc.

References gem5::bits().

◆ genInvalidVector()

uint32_t gem5::MipsISA::genInvalidVector ( uint32_t fcsr_bits )

Definition at line 132 of file utility.cc.

References Cause_Field, Flag_Field, and Invalid.

◆ getCauseIP()

uint8_t gem5::MipsISA::getCauseIP ( ThreadContext * tc )

inlinestatic

Definition at line 64 of file interrupts.cc.

References gem5::MipsISA::misc_reg::Cause, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::MipsISA::Interrupts::clear(), gem5::MipsISA::Interrupts::interruptsPending(), and gem5::MipsISA::Interrupts::post().

◆ getCondCode()

bool gem5::MipsISA::getCondCode	(	uint32_t	fcsr,
		int	cc_idx )

Definition at line 112 of file utility.cc.

References gem5::ArmISA::shift.

◆ getTargetThread()

template<class TC>

unsigned gem5::MipsISA::getTargetThread ( TC * tc )

inline

Definition at line 125 of file mt.hh.

References gem5::MipsISA::misc_reg::VpeControl.

◆ getVirtProcNum()

template<class TC>

unsigned gem5::MipsISA::getVirtProcNum ( TC * tc )

inline

Definition at line 117 of file mt.hh.

References gem5::MipsISA::misc_reg::TcBind.

◆ haltThread()

template<class TC>

void gem5::MipsISA::haltThread ( TC * tc )

inline

Definition at line 133 of file mt.hh.

References gem5::ArmISA::as, gem5::curTick(), pc, gem5::MipsISA::misc_reg::TcRestart, and warn.

Referenced by gem5::MipsISA::ISA::updateCPU().

◆ intRegClass()

RegClass gem5::MipsISA::intRegClass	(	IntRegClass	,
		IntRegClassName	,
		int_reg::NumRegs	,
		debug::IntRegs	)

inlineconstexpr

References gem5::IntRegClass, gem5::IntRegClassName, and gem5::MipsISA::int_reg::NumRegs.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), forkThread(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::MipsISA::ISA::ISA(), and gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs().

◆ isNan()

bool gem5::MipsISA::isNan	(	void *	val_ptr,
		int	size )

Definition at line 146 of file utility.cc.

References gem5::bits(), and panic.

◆ isQnan()

bool gem5::MipsISA::isQnan	(	void *	val_ptr,
		int	size )

Definition at line 169 of file utility.cc.

References gem5::bits(), and panic.

◆ isSnan()

bool gem5::MipsISA::isSnan	(	void *	val_ptr,
		int	size )

Definition at line 191 of file utility.cc.

References gem5::bits(), and panic.

◆ miscRegClass()

RegClass gem5::MipsISA::miscRegClass	(	MiscRegClass	,
		MiscRegClassName	,
		misc_reg::NumRegs	,
		debug::MiscRegs	)

inlineconstexpr

References gem5::MiscRegClass, gem5::MiscRegClassName, and gem5::MipsISA::misc_reg::NumRegs.

Referenced by forkThread(), gem5::MipsISA::ISA::ISA(), and yieldThread().

◆ readDSPControl()

uint32_t gem5::MipsISA::readDSPControl	(	uint32_t *	dspctl,
		uint32_t	mask )

Definition at line 1178 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, DSP_SCOUNT, and mask.

◆ readRegOtherThread() [1/2]

RegVal gem5::MipsISA::readRegOtherThread	(	ExecContext *	xc,
		const RegId &	reg,
		ThreadID	tid = InvalidThreadID )

inlinestatic

Definition at line 102 of file mt.hh.

References gem5::InvalidThreadID, readRegOtherThread(), gem5::X86ISA::reg, and gem5::ExecContext::tcBase().

◆ readRegOtherThread() [2/2]

RegVal gem5::MipsISA::readRegOtherThread	(	ThreadContext *	tc,
		const RegId &	reg,
		ThreadID	tid = InvalidThreadID )

inlinestatic

Definition at line 58 of file mt.hh.

References gem5::FloatRegClass, gem5::BaseCPU::getContext(), gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::getReg(), gem5::IntRegClass, gem5::InvalidThreadID, gem5::MiscRegClass, panic, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

Referenced by forkThread(), readRegOtherThread(), and yieldThread().

◆ restoreThread()

template<class TC>

void gem5::MipsISA::restoreThread ( TC * tc )

inline

Definition at line 152 of file mt.hh.

References gem5::curTick(), gem5::MipsISA::misc_reg::TcRestart, and warn.

Referenced by gem5::MipsISA::ISA::updateCPU().

◆ roundFP()

double gem5::MipsISA::roundFP	(	double	val,
		int	digits )

Definition at line 94 of file utility.cc.

References gem5::X86ISA::val.

◆ RoundPage()

Addr gem5::MipsISA::RoundPage ( Addr addr )

inline

Definition at line 75 of file utility.hh.

References gem5::X86ISA::addr, and PageBytes.

◆ setCauseIP()

void gem5::MipsISA::setCauseIP	(	ThreadContext *	tc,
		uint8_t	val )

inlinestatic

Definition at line 71 of file interrupts.cc.

References gem5::MipsISA::misc_reg::Cause, gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscRegNoEffect(), and gem5::X86ISA::val.

Referenced by gem5::MipsISA::Interrupts::clear(), gem5::MipsISA::Interrupts::clearAll(), gem5::MipsISA::Interrupts::interruptsPending(), and gem5::MipsISA::Interrupts::post().

◆ setRegOtherThread() [1/2]

void gem5::MipsISA::setRegOtherThread	(	ExecContext *	xc,
		const RegId &	reg,
		RegVal	val,
		ThreadID	tid = InvalidThreadID )

inlinestatic

Definition at line 109 of file mt.hh.

References gem5::InvalidThreadID, gem5::X86ISA::reg, setRegOtherThread(), gem5::ExecContext::tcBase(), and gem5::X86ISA::val.

◆ setRegOtherThread() [2/2]

void gem5::MipsISA::setRegOtherThread	(	ThreadContext *	tc,
		const RegId &	reg,
		RegVal	val,
		ThreadID	tid = InvalidThreadID )

inlinestatic

Definition at line 80 of file mt.hh.

References gem5::FloatRegClass, gem5::BaseCPU::getContext(), gem5::ThreadContext::getCpuPtr(), gem5::IntRegClass, gem5::InvalidThreadID, gem5::MiscRegClass, panic, gem5::X86ISA::reg, gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setReg(), and gem5::X86ISA::val.

Referenced by forkThread(), and setRegOtherThread().

◆ setThreadAreaFunc()

SyscallReturn gem5::MipsISA::setThreadAreaFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	addr )

static

Definition at line 165 of file se_workload.cc.

References gem5::X86ISA::addr, gem5::ThreadContext::setMiscRegNoEffect(), and gem5::MipsISA::misc_reg::TpValue.

◆ signExtend()

uint64_t gem5::MipsISA::signExtend	(	uint64_t	value,
		int32_t	signpos )

Definition at line 113 of file dsp.cc.

References SIMD_NBITS.

Referenced by simdUnpack().

◆ simdPack()

void gem5::MipsISA::simdPack	(	uint64_t *	values_ptr,
		int32_t *	reg,
		int32_t	fmt )

Definition at line 1127 of file dsp.cc.

References gem5::bits(), i, gem5::X86ISA::reg, SIMD_NBITS, and SIMD_NVALS.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ simdUnpack()

void gem5::MipsISA::simdUnpack	(	int32_t	reg,
		uint64_t *	values_ptr,
		int32_t	fmt,
		int32_t	sign )

Definition at line 1139 of file dsp.cc.

References gem5::bits(), i, gem5::X86ISA::reg, SIGNED, signExtend(), SIMD_NBITS, SIMD_NVALS, and UNSIGNED.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ SubBitUnion() [1/3]

gem5::MipsISA::SubBitUnion	(	ejtagVer	,
		17	,
		15	)

Referenced by EndBitUnion(), SubBitUnion(), and SubBitUnion().

◆ SubBitUnion() [2/3]

gem5::MipsISA::SubBitUnion	(	im	,
		15	,
		8	)

References SubBitUnion().

◆ SubBitUnion() [3/3]

gem5::MipsISA::SubBitUnion	(	ip	,
		15	,
		8	)

References SubBitUnion().

◆ sys_getsysinfoFunc()

SyscallReturn gem5::MipsISA::sys_getsysinfoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	op,
		unsigned	bufPtr,
		unsigned	nbytes )

static

Target sys_getsysyinfo() handler.

Even though this call is borrowed from Tru64, the subcases that get used appear to be different in practice from those used by Tru64 processes.

Definition at line 118 of file se_workload.cc.

References gem5::X86ISA::op.

◆ sys_setsysinfoFunc()

SyscallReturn gem5::MipsISA::sys_setsysinfoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	op,
		VPtr<>	bufPtr,
		unsigned	nbytes )

static

Target sys_setsysinfo() handler.

Definition at line 141 of file se_workload.cc.

References DPRINTFR, gem5::letoh(), and gem5::X86ISA::op.

◆ truncFP()

double gem5::MipsISA::truncFP ( double val )

Definition at line 105 of file utility.cc.

References gem5::X86ISA::val.

◆ TruncPage()

Addr gem5::MipsISA::TruncPage ( Addr addr )

inline

Definition at line 69 of file utility.hh.

References gem5::X86ISA::addr, and PageBytes.

◆ unameFunc()

SyscallReturn gem5::MipsISA::unameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< Linux::utsname >	name )

static

Target uname() handler.

Definition at line 101 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

◆ updateStatusView()

template<class TC>

void gem5::MipsISA::updateStatusView ( TC * tc )

inline

Definition at line 298 of file mt.hh.

References gem5::MipsISA::misc_reg::Status, gem5::ArmISA::status, and gem5::MipsISA::misc_reg::TcStatus.

◆ updateTCStatusView()

template<class TC>

void gem5::MipsISA::updateTCStatusView ( TC * tc )

inline

Definition at line 316 of file mt.hh.

References gem5::MipsISA::misc_reg::Status, gem5::ArmISA::status, and gem5::MipsISA::misc_reg::TcStatus.

◆ writeDSPControl()

void gem5::MipsISA::writeDSPControl	(	uint32_t *	dspctl,
		uint32_t	value,
		uint32_t	mask )

Definition at line 1161 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, DSP_SCOUNT, and mask.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspShll(), and dspSub().

◆ yieldThread()

template<class TC>

int gem5::MipsISA::yieldThread	(	TC *	tc,
		Fault &	fault,
		int	src_reg,
		uint32_t	yield_mask )

Definition at line 235 of file mt.hh.

References gem5::curTick(), miscRegClass(), gem5::MipsISA::misc_reg::MvpConf0, readRegOtherThread(), gem5::MipsISA::misc_reg::TcBind, gem5::MipsISA::misc_reg::TcHalt, gem5::MipsISA::misc_reg::TcStatus, gem5::MipsISA::misc_reg::VpeControl, and warn.

Variable Documentation

◆ a

Bitfield<13> gem5::MipsISA::a

Definition at line 92 of file mt_constants.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ a0

Bitfield<20, 18> gem5::MipsISA::a0

Definition at line 79 of file mt_constants.hh.

Referenced by gem5::ArmISA::add128(), gem5::ArmISA::cmp128(), gem5::ArmISA::mul62x62(), and gem5::ArmISA::sub128().

◆ ar

Bitfield<12, 10> gem5::MipsISA::ar

Definition at line 225 of file pra_constants.hh.

◆ aseDn

Bitfield<12, 8> gem5::MipsISA::aseDn

Definition at line 83 of file pra_constants.hh.

◆ aseUp

gem5::MipsISA::aseUp

Definition at line 79 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > gem5::MipsISA::asid

Definition at line 85 of file dt_constants.hh.

Referenced by EndBitUnion().

◆ asidM

Bitfield<20, 13> gem5::MipsISA::asidM

Definition at line 84 of file dt_constants.hh.

◆ at

Bitfield<14, 13> gem5::MipsISA::at

Definition at line 224 of file pra_constants.hh.

◆ ate

Bitfield<27> gem5::MipsISA::ate

Definition at line 108 of file dt_constants.hh.

◆ badVPN2

Bitfield<22, 4> gem5::MipsISA::badVPN2

Definition at line 67 of file pra_constants.hh.

◆ be

Bitfield<15> gem5::MipsISA::be

Definition at line 223 of file pra_constants.hh.

Referenced by gem5::Request::setByteEnable().

◆ bev

Bitfield<22> gem5::MipsISA::bev

Definition at line 117 of file pra_constants.hh.

◆ bpc0

Bitfield<2, 0> gem5::MipsISA::bpc0

Definition at line 117 of file dt_constants.hh.

◆ bpc1

Bitfield<5, 3> gem5::MipsISA::bpc1

Definition at line 116 of file dt_constants.hh.

◆ bpc10

Bitfield<5, 3> gem5::MipsISA::bpc10

Definition at line 125 of file dt_constants.hh.

◆ bpc11

Bitfield<8, 6> gem5::MipsISA::bpc11

Definition at line 124 of file dt_constants.hh.

◆ bpc12

Bitfield<11, 9> gem5::MipsISA::bpc12

Definition at line 123 of file dt_constants.hh.

◆ bpc13

Bitfield<14, 12> gem5::MipsISA::bpc13

Definition at line 122 of file dt_constants.hh.

◆ bpc14

gem5::MipsISA::bpc14

Definition at line 121 of file dt_constants.hh.

◆ bpc2

Bitfield<8, 6> gem5::MipsISA::bpc2

Definition at line 115 of file dt_constants.hh.

◆ bpc3

Bitfield<11, 9> gem5::MipsISA::bpc3

Definition at line 114 of file dt_constants.hh.

◆ bpc4

Bitfield<14, 12> gem5::MipsISA::bpc4

Definition at line 113 of file dt_constants.hh.

◆ bpc5

Bitfield<17, 15> gem5::MipsISA::bpc5

Definition at line 112 of file dt_constants.hh.

◆ bpc6

Bitfield<20, 18> gem5::MipsISA::bpc6

Definition at line 111 of file dt_constants.hh.

◆ bpc7

Bitfield<23, 21> gem5::MipsISA::bpc7

Definition at line 110 of file dt_constants.hh.

◆ bpc8

Bitfield<26, 24> gem5::MipsISA::bpc8

Definition at line 109 of file dt_constants.hh.

◆ bpc9

Bitfield<2, 0> gem5::MipsISA::bpc9

Definition at line 126 of file dt_constants.hh.

◆ c

Bitfield<5, 3> gem5::MipsISA::c

Definition at line 59 of file pra_constants.hh.

◆ c2

Bitfield<6> gem5::MipsISA::c2

Definition at line 241 of file pra_constants.hh.

Referenced by gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hash2(), gem5::mulUnsignedManual(), gem5::MemCmd::operator!=(), and gem5::MemCmd::operator==().

◆ ca

Bitfield<2> gem5::MipsISA::ca

Definition at line 245 of file pra_constants.hh.

◆ cacheep

Bitfield<22> gem5::MipsISA::cacheep

Definition at line 51 of file dt_constants.hh.

◆ ce

Bitfield<29, 28> gem5::MipsISA::ce

Definition at line 180 of file pra_constants.hh.

Referenced by gem5::DmaPort::DmaReqState::DmaReqState().

◆ coId

Bitfield<23, 16> gem5::MipsISA::coId

Definition at line 205 of file pra_constants.hh.

◆ conutdm

Bitfield<25> gem5::MipsISA::conutdm

Definition at line 48 of file dt_constants.hh.

◆ coOp

gem5::MipsISA::coOp

Definition at line 204 of file pra_constants.hh.

◆ cpuid

Bitfield<28, 21> gem5::MipsISA::cpuid

Definition at line 95 of file dt_constants.hh.

Referenced by gem5::Iob::readJBus(), gem5::X86KvmCPU::setCPUID(), gem5::X86KvmCPU::setCPUID(), gem5::X86KvmCPU::updateCPUID(), gem5::pseudo_inst::wakeCPU(), and gem5::Iob::writeJBus().

◆ cpuNum

Bitfield<9, 9> gem5::MipsISA::cpuNum

Definition at line 215 of file pra_constants.hh.

◆ css

Bitfield<3, 0> gem5::MipsISA::css

Definition at line 163 of file pra_constants.hh.

◆ cu0

Bitfield<28> gem5::MipsISA::cu0

Definition at line 110 of file pra_constants.hh.

◆ cu1

Bitfield<29> gem5::MipsISA::cu1

Definition at line 109 of file pra_constants.hh.

◆ cu2

Bitfield<30> gem5::MipsISA::cu2

Definition at line 108 of file pra_constants.hh.

◆ cu3

Bitfield<31> gem5::MipsISA::cu3

Definition at line 107 of file pra_constants.hh.

◆ curTC

gem5::MipsISA::curTC

Definition at line 78 of file mt_constants.hh.

◆ curVPE

Bitfield<3, 0> gem5::MipsISA::curVPE

Definition at line 81 of file mt_constants.hh.

◆ d

Bitfield< 2 > gem5::MipsISA::d

Definition at line 79 of file dt_constants.hh.

◆ da

Bitfield< 9, 7 > gem5::MipsISA::da

Definition at line 91 of file mt_constants.hh.

◆ dbp

Bitfield<1> gem5::MipsISA::dbp

Definition at line 70 of file dt_constants.hh.

◆ dbusep

Bitfield<21> gem5::MipsISA::dbusep

Definition at line 52 of file dt_constants.hh.

◆ dc

Bitfield<27> gem5::MipsISA::dc

Definition at line 181 of file pra_constants.hh.

◆ dcs

Bitfield<17> gem5::MipsISA::dcs

Definition at line 71 of file mt_constants.hh.

◆ ddbl

Bitfield<2> gem5::MipsISA::ddbl

Definition at line 69 of file dt_constants.hh.

◆ ddblImpr

Bitfield<18> gem5::MipsISA::ddblImpr

Definition at line 55 of file dt_constants.hh.

◆ ddbs

Bitfield<3> gem5::MipsISA::ddbs

Definition at line 68 of file dt_constants.hh.

◆ ddbsImpr

Bitfield<19> gem5::MipsISA::ddbsImpr

Definition at line 54 of file dt_constants.hh.

◆ dexcCode

gem5::MipsISA::dexcCode

Definition at line 61 of file dt_constants.hh.

◆ dib

Bitfield<4> gem5::MipsISA::dib

Definition at line 67 of file dt_constants.hh.

◆ dibimpr

Bitfield<6> gem5::MipsISA::dibimpr

Definition at line 65 of file dt_constants.hh.

◆ dint

Bitfield<5> gem5::MipsISA::dint

Definition at line 66 of file dt_constants.hh.

◆ dl

Bitfield<12, 10> gem5::MipsISA::dl

Definition at line 239 of file pra_constants.hh.

◆ dm

Bitfield<30> gem5::MipsISA::dm

Definition at line 43 of file dt_constants.hh.

Referenced by gem5::X86ISA::Interrupts::raiseInterruptPin().

◆ doze

Bitfield<27> gem5::MipsISA::doze

Definition at line 46 of file dt_constants.hh.

◆ dq

Bitfield<2> gem5::MipsISA::dq

Definition at line 131 of file dt_constants.hh.

Referenced by gem5::ScheduleStage::ScheduleStage().

◆ ds

Bitfield<15, 13> gem5::MipsISA::ds

Definition at line 238 of file pra_constants.hh.

Referenced by gem5::X86ISA::FsWorkload::initState(), and gem5::X86ISA::X86_64Process::initState().

◆ DSP_CTL_MASK

const uint32_t gem5::MipsISA::DSP_CTL_MASK[DSP_NUM_FIELDS]

Initial value:

=
{ 0x0000003f, 0x00001f80, 0x00002000,
  0x00ff0000, 0x0f000000, 0x00004000 }

Definition at line 90 of file dsp.hh.

Referenced by readDSPControl(), and writeDSPControl().

◆ DSP_CTL_POS

const uint32_t gem5::MipsISA::DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }

Definition at line 89 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPick(), dspShll(), and dspSub().

◆ dspp

Bitfield<10> gem5::MipsISA::dspp

Definition at line 265 of file pra_constants.hh.

◆ dss

Bitfield<0> gem5::MipsISA::dss

Definition at line 71 of file dt_constants.hh.

◆ dt

Bitfield<20> gem5::MipsISA::dt

Definition at line 89 of file mt_constants.hh.

◆ e

Bitfield< 28 > gem5::MipsISA::e

Definition at line 80 of file dt_constants.hh.

Referenced by EndBitUnion().

◆ eb

Bitfield<25> gem5::MipsISA::eb

Definition at line 315 of file pra_constants.hh.

◆ ec

Bitfield<30> gem5::MipsISA::ec

Definition at line 310 of file pra_constants.hh.

◆ ed

Bitfield<29> gem5::MipsISA::ed

Definition at line 311 of file pra_constants.hh.

◆ ee

Bitfield<26> gem5::MipsISA::ee

Definition at line 314 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> gem5::MipsISA::eicss

Definition at line 157 of file pra_constants.hh.

◆ ejtagVer0

Bitfield<15> gem5::MipsISA::ejtagVer0

Definition at line 59 of file dt_constants.hh.

◆ ejtagVer1

Bitfield<16> gem5::MipsISA::ejtagVer1

Definition at line 58 of file dt_constants.hh.

◆ elpa

Bitfield<29> gem5::MipsISA::elpa

Definition at line 80 of file pra_constants.hh.

◆ ep

Bitfield<1> gem5::MipsISA::ep

Definition at line 246 of file pra_constants.hh.

Referenced by gem5::SMMUProcess::scheduleWakeup(), and gem5::TesterThread::~TesterThread().

◆ erl

Bitfield<2> gem5::MipsISA::erl

Definition at line 140 of file pra_constants.hh.

◆ es

Bitfield<27> gem5::MipsISA::es

Definition at line 313 of file pra_constants.hh.

◆ esp

Bitfield<28> gem5::MipsISA::esp

Definition at line 81 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> gem5::MipsISA::ess

Definition at line 159 of file pra_constants.hh.

◆ et

Bitfield<28> gem5::MipsISA::et

Definition at line 312 of file pra_constants.hh.

◆ event

Bitfield<10, 5> gem5::MipsISA::event

Definition at line 300 of file pra_constants.hh.

◆ evp

Bitfield<0> gem5::MipsISA::evp

Definition at line 45 of file mt_constants.hh.

◆ excCode

Bitfield<6, 2> gem5::MipsISA::excCode

Definition at line 199 of file pra_constants.hh.

Referenced by gem5::MipsISA::MipsFaultBase::setExceptionState(), and gem5::MipsISA::TlbFault< T >::setTlbExceptionState().

◆ exceptionBase

gem5::MipsISA::exceptionBase

Definition at line 213 of file pra_constants.hh.

◆ excpt

Bitfield<18, 16> gem5::MipsISA::excpt

Definition at line 61 of file mt_constants.hh.

◆ exl

Bitfield< 0 > gem5::MipsISA::exl

Definition at line 141 of file pra_constants.hh.

◆ fill

Bitfield< 61, 40 > gem5::MipsISA::fill

Definition at line 57 of file pra_constants.hh.

Referenced by gem5::FrameBuffer::clear(), gem5::RegisterBank< BankByteOrder >::RegisterRoFill::read(), and gem5::RegisterBank< BankByteOrder >::RegisterRoFill::read().

◆ FIXED_B_SMAX

const uint64_t gem5::MipsISA::FIXED_B_SMAX = 0x000000000000007fULL

Definition at line 112 of file dsp.hh.

◆ FIXED_B_SMIN

const uint64_t gem5::MipsISA::FIXED_B_SMIN = 0xffffffffffffff80ULL

Definition at line 126 of file dsp.hh.

◆ FIXED_B_UMAX

const uint64_t gem5::MipsISA::FIXED_B_UMAX = 0x00000000000000ffULL

Definition at line 116 of file dsp.hh.

◆ FIXED_B_UMIN

const uint64_t gem5::MipsISA::FIXED_B_UMIN = 0x0000000000000000ULL

Definition at line 130 of file dsp.hh.

◆ FIXED_H_SMAX

const uint64_t gem5::MipsISA::FIXED_H_SMAX = 0x0000000000007fffULL

Definition at line 111 of file dsp.hh.

◆ FIXED_H_SMIN

const uint64_t gem5::MipsISA::FIXED_H_SMIN = 0xffffffffffff8000ULL

Definition at line 125 of file dsp.hh.

◆ FIXED_H_UMAX

const uint64_t gem5::MipsISA::FIXED_H_UMAX = 0x000000000000ffffULL

Definition at line 115 of file dsp.hh.

◆ FIXED_H_UMIN

const uint64_t gem5::MipsISA::FIXED_H_UMIN = 0x0000000000000000ULL

Definition at line 129 of file dsp.hh.

◆ FIXED_L_SMAX

const uint64_t gem5::MipsISA::FIXED_L_SMAX = 0x7fffffffffffffffULL

Definition at line 109 of file dsp.hh.

◆ FIXED_L_SMIN

const uint64_t gem5::MipsISA::FIXED_L_SMIN = 0x8000000000000000ULL

Definition at line 123 of file dsp.hh.

◆ FIXED_L_UMAX

const uint64_t gem5::MipsISA::FIXED_L_UMAX = 0xffffffffffffffffULL

Definition at line 113 of file dsp.hh.

◆ FIXED_L_UMIN

const uint64_t gem5::MipsISA::FIXED_L_UMIN = 0x0000000000000000ULL

Definition at line 127 of file dsp.hh.

◆ FIXED_SMAX

const uint64_t gem5::MipsISA::FIXED_SMAX[SIMD_NUM_FMTS]

Initial value:

=

{ FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX }

gem5::MipsISA::FIXED_W_SMAX

const uint64_t FIXED_W_SMAX

Definition dsp.hh:110

gem5::MipsISA::FIXED_B_SMAX

const uint64_t FIXED_B_SMAX

Definition dsp.hh:112

gem5::MipsISA::FIXED_H_SMAX

const uint64_t FIXED_H_SMAX

Definition dsp.hh:111

gem5::MipsISA::FIXED_L_SMAX

const uint64_t FIXED_L_SMAX

Definition dsp.hh:109

Definition at line 117 of file dsp.hh.

Referenced by checkOverflow(), dspAbs(), dspDpaq(), dspDpsq(), dspExtr(), dspMaq(), dspMulq(), dspMulsaq(), and dspSaturate().

◆ FIXED_SMIN

const uint64_t gem5::MipsISA::FIXED_SMIN[SIMD_NUM_FMTS]

Initial value:

=

{ FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN }

gem5::MipsISA::FIXED_B_SMIN

const uint64_t FIXED_B_SMIN

Definition dsp.hh:126

gem5::MipsISA::FIXED_H_SMIN

const uint64_t FIXED_H_SMIN

Definition dsp.hh:125

gem5::MipsISA::FIXED_W_SMIN

const uint64_t FIXED_W_SMIN

Definition dsp.hh:124

gem5::MipsISA::FIXED_L_SMIN

const uint64_t FIXED_L_SMIN

Definition dsp.hh:123

Definition at line 131 of file dsp.hh.

Referenced by checkOverflow(), dspAbs(), dspDpaq(), dspDpsq(), dspMaq(), dspMulq(), dspMulsaq(), and dspSaturate().

◆ FIXED_UMAX

const uint64_t gem5::MipsISA::FIXED_UMAX[SIMD_NUM_FMTS]

Initial value:

=

{ FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX }

gem5::MipsISA::FIXED_H_UMAX

const uint64_t FIXED_H_UMAX

Definition dsp.hh:115

gem5::MipsISA::FIXED_W_UMAX

const uint64_t FIXED_W_UMAX

Definition dsp.hh:114

gem5::MipsISA::FIXED_L_UMAX

const uint64_t FIXED_L_UMAX

Definition dsp.hh:113

gem5::MipsISA::FIXED_B_UMAX

const uint64_t FIXED_B_UMAX

Definition dsp.hh:116

Definition at line 119 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_UMIN

const uint64_t gem5::MipsISA::FIXED_UMIN[SIMD_NUM_FMTS]

Initial value:

=

{ FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN }

gem5::MipsISA::FIXED_W_UMIN

const uint64_t FIXED_W_UMIN

Definition dsp.hh:128

gem5::MipsISA::FIXED_B_UMIN

const uint64_t FIXED_B_UMIN

Definition dsp.hh:130

gem5::MipsISA::FIXED_L_UMIN

const uint64_t FIXED_L_UMIN

Definition dsp.hh:127

gem5::MipsISA::FIXED_H_UMIN

const uint64_t FIXED_H_UMIN

Definition dsp.hh:129

Definition at line 133 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_W_SMAX

const uint64_t gem5::MipsISA::FIXED_W_SMAX = 0x000000007fffffffULL

Definition at line 110 of file dsp.hh.

◆ FIXED_W_SMIN

const uint64_t gem5::MipsISA::FIXED_W_SMIN = 0xffffffff80000000ULL

Definition at line 124 of file dsp.hh.

◆ FIXED_W_UMAX

const uint64_t gem5::MipsISA::FIXED_W_UMAX = 0x00000000ffffffffULL

Definition at line 114 of file dsp.hh.

◆ FIXED_W_UMIN

const uint64_t gem5::MipsISA::FIXED_W_UMIN = 0x0000000000000000ULL

Definition at line 128 of file dsp.hh.

◆ fp

Bitfield<0> gem5::MipsISA::fp

Definition at line 247 of file pra_constants.hh.

◆ fr

Bitfield<26> gem5::MipsISA::fr

Definition at line 113 of file pra_constants.hh.

◆ g

Bitfield< 30 > gem5::MipsISA::g

Definition at line 86 of file dt_constants.hh.

Referenced by gem5::BaseGdbRegCache::BaseGdbRegCache(), EndBitUnion(), gem5::branch_prediction::MultiperspectivePerceptron::getIndex(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::getIndex(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::statistics::Group::preDumpStats(), gem5::statistics::Group::regStats(), gem5::statistics::Group::resetStats(), gem5::statistics::Group::resolveStat(), TEST(), TEST(), gem5::BaseRemoteGDB::TrapEvent::TrapEvent(), and gem5::UncontendedMutex::unlock().

◆ gs

Bitfield<28> gem5::MipsISA::gs

Definition at line 51 of file mt_constants.hh.

◆ halt

Bitfield<26> gem5::MipsISA::halt

Definition at line 47 of file dt_constants.hh.

◆ hss

gem5::MipsISA::hss

Definition at line 155 of file pra_constants.hh.

◆ i

Bitfield< 2 > gem5::MipsISA::i

◆ ia

Bitfield<18, 16> gem5::MipsISA::ia

Definition at line 237 of file pra_constants.hh.

Referenced by gem5::networking::operator<<().

◆ ibusep

Bitfield<24> gem5::MipsISA::ibusep

Definition at line 49 of file dt_constants.hh.

◆ ics

Bitfield<16> gem5::MipsISA::ics

Definition at line 72 of file mt_constants.hh.

◆ ie

Bitfield< 4 > gem5::MipsISA::ie

Definition at line 142 of file pra_constants.hh.

Referenced by gem5::SparcISA::EndBitUnion(), and gem5::LupioTMR::lupioTMRCallback().

◆ iexi

Bitfield<20, 19> gem5::MipsISA::iexi

Definition at line 53 of file dt_constants.hh.

◆ il

Bitfield<21, 19> gem5::MipsISA::il

Definition at line 236 of file pra_constants.hh.

◆ im0

Bitfield<8> gem5::MipsISA::im0

Definition at line 132 of file pra_constants.hh.

◆ im1

Bitfield<9> gem5::MipsISA::im1

Definition at line 131 of file pra_constants.hh.

◆ im2

Bitfield<10> gem5::MipsISA::im2

Definition at line 130 of file pra_constants.hh.

◆ im3

Bitfield<11> gem5::MipsISA::im3

Definition at line 129 of file pra_constants.hh.

◆ im4

Bitfield<12> gem5::MipsISA::im4

Definition at line 128 of file pra_constants.hh.

◆ im5

Bitfield<13> gem5::MipsISA::im5

Definition at line 127 of file pra_constants.hh.

◆ im6

Bitfield<14> gem5::MipsISA::im6

Definition at line 126 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > gem5::MipsISA::impl

Definition at line 90 of file mt_constants.hh.

Referenced by gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::buildDispatcher(), gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::buildDumper(), EndBitUnion(), and gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::wrapImpl().

◆ index

Bitfield< 22, 0 > gem5::MipsISA::index

Definition at line 47 of file pra_constants.hh.

◆ io

Bitfield<26> gem5::MipsISA::io

Definition at line 78 of file dt_constants.hh.

Referenced by gem5::PciMemBar::EndSubBitUnion().

◆ ip0

Bitfield<8> gem5::MipsISA::ip0

Definition at line 196 of file pra_constants.hh.

◆ ip1

Bitfield<9> gem5::MipsISA::ip1

Definition at line 195 of file pra_constants.hh.

◆ ip2

Bitfield<10> gem5::MipsISA::ip2

Definition at line 194 of file pra_constants.hh.

◆ ip3

Bitfield<11> gem5::MipsISA::ip3

Definition at line 193 of file pra_constants.hh.

◆ ip4

Bitfield<12> gem5::MipsISA::ip4

Definition at line 192 of file pra_constants.hh.

◆ ip5

Bitfield<13> gem5::MipsISA::ip5

Definition at line 191 of file pra_constants.hh.

◆ ip6

Bitfield<14> gem5::MipsISA::ip6

Definition at line 190 of file pra_constants.hh.

Referenced by gem5::networking::__tu_cksum6(), gem5::networking::hsplit(), gem5::IGbE::RxDescCache::pktComplete(), and gem5::IGbE::TxDescCache::pktComplete().

◆ ipl

Bitfield<15, 10> gem5::MipsISA::ipl

Definition at line 123 of file pra_constants.hh.

◆ ippci

Bitfield<28, 26> gem5::MipsISA::ippci

Definition at line 147 of file pra_constants.hh.

◆ ipti

gem5::MipsISA::ipti

Definition at line 146 of file pra_constants.hh.

◆ is

Bitfield<24, 22> gem5::MipsISA::is

Definition at line 235 of file pra_constants.hh.

Referenced by getContents(), gem5::CheckerCPU::getRegOperand(), getString(), gem5::X86ISA::EmuLinux::pageFault(), gem5::TrafficGen::parseConfig(), gem5::CheckerCPU::setRegOperand(), gem5::CheckerCPU::setRegOperand(), TEST_F(), TEST_F(), and gem5::RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >::unserialize().

◆ iv

Bitfield<23> gem5::MipsISA::iv

Definition at line 184 of file pra_constants.hh.

◆ ixmt

Bitfield<10> gem5::MipsISA::ixmt

Definition at line 94 of file mt_constants.hh.

◆ k

Bitfield< 1 > gem5::MipsISA::k

Definition at line 81 of file dt_constants.hh.

Referenced by gem5::MipsISA::ISA::clear(), gem5::ruby::Profiler::collateStats(), gem5::debug::CompoundFlag::disable(), gem5::debug::CompoundFlag::enable(), gem5::SparcISA::TlbMap::erase(), gem5::VegaISA::Inst_VOP2__V_MADAK_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MADMK_F32::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA< 1, 4, 4, 1, 16, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_4X4X1_16B_F32 >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< 16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8 >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_MXFP< 16, 16, 16, 1, AMDGPU::mxfloat16, &MNEM__V_MFMA_F32_16X16X16_F16 >::execute(), gem5::ruby::Topology::extend_shortest_path(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::AMDGPUDevice::AddrRangeHasher::operator()(), gem5::ComputeUnit::startWavefront(), gem5::CompressedTags::tagsInit(), gem5::SectorTags::tagsInit(), TEST(), TEST(), TEST(), and gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::ThreadData().

◆ k0

Bitfield<2, 0> gem5::MipsISA::k0

Definition at line 229 of file pra_constants.hh.

Referenced by gem5::ArmISA::addPAC(), and gem5::ArmISA::auth().

◆ k23

Bitfield<30, 28> gem5::MipsISA::k23

Definition at line 220 of file pra_constants.hh.

◆ ksu

Bitfield<4, 3> gem5::MipsISA::ksu

Definition at line 137 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> gem5::MipsISA::ku

Definition at line 221 of file pra_constants.hh.

◆ l

Bitfield<5> gem5::MipsISA::l

Definition at line 323 of file pra_constants.hh.

Referenced by gem5::ProbePointArg< PacketInfo >::addListener(), gem5::CacheBlk::checkWrite(), gem5::CacheBlk::clearLoadLocks(), gem5::ruby::Topology::createLinks(), gem5::TapListener::Event::Event(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), gem5::BaseArmKvmCPU::ioctlRun(), gem5::MemChecker::ByteTracker::lastCompletedTransaction(), gem5::o3::LSQUnit::LSQUnit(), gem5::ruby::Topology::makeLink(), gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo(), gem5::ProbePointArg< PacketInfo >::notify(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::PCEventQueue::MapCompare::operator()(), gem5::PCEventQueue::MapCompare::operator()(), gem5::statistics::operator*(), gem5::operator+(), gem5::statistics::operator+(), gem5::operator-(), gem5::statistics::operator-(), gem5::statistics::operator-(), gem5::statistics::operator/(), gem5::operator<(), gem5::operator<(), gem5::operator<=(), gem5::operator<=(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator>(), gem5::operator>(), gem5::ruby::operator>(), gem5::operator>=(), gem5::operator>=(), gem5::MathExpr::parse(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::AMDMMIOReader::readMMIOTrace(), gem5::ruby::RubyPort::PioResponsePort::recvAtomic(), gem5::ruby::RubyPort::PioResponsePort::recvTimingReq(), gem5::ProbePointArg< PacketInfo >::removeListener(), gem5::memory::PhysicalMemory::serialize(), SwitchingFiber::SwitchingFiber(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), RegisterBankTest::TestReg::TestReg(), gem5::CacheBlk::trackLoadLocked(), gem5::statistics::VectorProxy< Derived >::VectorProxy(), gem5::WalkCache::WalkCacheStats::WalkCacheStats(), gem5::CoherentXBar::~CoherentXBar(), and gem5::NoncoherentXBar::~NoncoherentXBar().

◆ lpa

Bitfield<7> gem5::MipsISA::lpa

Definition at line 267 of file pra_constants.hh.

◆ lsnm

Bitfield<28> gem5::MipsISA::lsnm

Definition at line 45 of file dt_constants.hh.

◆ mask

Bitfield< 11, 3 > gem5::MipsISA::mask

Definition at line 73 of file pra_constants.hh.

Referenced by gem5::MipsISA::ISA::configCP(), EndBitUnion(), EndBitUnion(), readDSPControl(), and writeDSPControl().

◆ maskx

Bitfield<12, 11> gem5::MipsISA::maskx

Definition at line 74 of file pra_constants.hh.

◆ MaxShadowRegSets

const int gem5::MipsISA::MaxShadowRegSets = 16

Definition at line 43 of file int.hh.

◆ mcheckep

Bitfield<23> gem5::MipsISA::mcheckep

Definition at line 50 of file dt_constants.hh.

◆ md

Bitfield<5> gem5::MipsISA::md

Definition at line 242 of file pra_constants.hh.

◆ MIPS32_QNAN

Definition faults.hh:71

Definition at line 69 of file faults.cc.

◆ MipsFault< NonMaskableInterrupt >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< NonMaskableInterrupt >::vals

Initial value:

=

{ "Non Maskable Interrupt", 0x000, ExcCodeDummy }

Definition at line 78 of file faults.cc.

◆ MipsFault< ReservedInstructionFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< ReservedInstructionFault >::vals

Initial value:

=

{ "Reserved Instruction Fault", 0x180, ExcCodeRI }

gem5::MipsISA::ExcCodeRI

@ ExcCodeRI

Definition faults.hh:64

Definition at line 51 of file faults.cc.

◆ MipsFault< ResetFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< ResetFault >::vals

Initial value:

=

{ "Reset Fault", 0x000, ExcCodeDummy }

Definition at line 72 of file faults.cc.

◆ MipsFault< SoftResetFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< SoftResetFault >::vals

Initial value:

=

{ "Soft Reset Fault", 0x000, ExcCodeDummy }

Definition at line 75 of file faults.cc.

◆ MipsFault< SystemCallFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< SystemCallFault >::vals

Initial value:

=

{ "Syscall", 0x180, ExcCodeSys }

gem5::MipsISA::ExcCodeSys

@ ExcCodeSys

Definition faults.hh:62

Definition at line 48 of file faults.cc.

◆ MipsFault< ThreadFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< ThreadFault >::vals

Initial value:

=

{ "Thread Fault", 0x180, ExcCodeDummy }

Definition at line 54 of file faults.cc.

◆ MipsFault< TlbInvalidFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< TlbInvalidFault >::vals

Initial value:

=

{ "Invalid TLB Entry Exception", 0x180, ExcCodeDummy }

Definition at line 90 of file faults.cc.

◆ MipsFault< TlbModifiedFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< TlbModifiedFault >::vals

Initial value:

=

{ "TLB Modified Exception", 0x180, ExcCodeMod }

gem5::MipsISA::ExcCodeMod

@ ExcCodeMod

Definition faults.hh:55

Definition at line 96 of file faults.cc.

◆ MipsFault< TlbRefillFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< TlbRefillFault >::vals

Initial value:

=

{ "TLB Refill Exception", 0x180, ExcCodeDummy }

Definition at line 93 of file faults.cc.

◆ MipsFault< TrapFault >::vals

template<>

MipsFaultBase::FaultVals gem5::MipsISA::MipsFault< TrapFault >::vals

Initial value:

=

{ "Trap", 0x180, ExcCodeTr }

gem5::MipsISA::ExcCodeTr

@ ExcCodeTr

Definition faults.hh:67

Definition at line 60 of file faults.cc.

◆ mmuSize

Bitfield<30, 25> gem5::MipsISA::mmuSize

Definition at line 234 of file pra_constants.hh.

◆ mode

Bitfield<11, 7> gem5::MipsISA::mode

Definition at line 98 of file dt_constants.hh.

Referenced by dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMuleq(), dspMuleu(), dspPrece(), gem5::MipsISA::TLB::finalizePhysical(), gem5::MipsISA::TLB::translateAtomic(), gem5::MipsISA::MMU::translateFunctional(), gem5::MipsISA::TLB::translateFunctional(), and gem5::MipsISA::TLB::translateTiming().

◆ mt

Bitfield< 2 > gem5::MipsISA::mt

Definition at line 226 of file pra_constants.hh.

◆ mvp

Bitfield<1> gem5::MipsISA::mvp

Definition at line 73 of file mt_constants.hh.

◆ mx

Bitfield<24> gem5::MipsISA::mx

Definition at line 115 of file pra_constants.hh.

◆ nmi

Bitfield<19> gem5::MipsISA::nmi

Definition at line 120 of file pra_constants.hh.

◆ nodcr

Bitfield<29> gem5::MipsISA::nodcr

Definition at line 44 of file dt_constants.hh.

◆ nosst

Bitfield<9> gem5::MipsISA::nosst

Definition at line 62 of file dt_constants.hh.

◆ offline

Bitfield<7> gem5::MipsISA::offline

Definition at line 64 of file dt_constants.hh.

◆ on

Bitfield<0> gem5::MipsISA::on

Definition at line 90 of file dt_constants.hh.

Referenced by sc_gem5::Scheduler::deschedule().

◆ p

Bitfield<0> gem5::MipsISA::p

Definition at line 326 of file pra_constants.hh.

◆ paco

Bitfield<0> gem5::MipsISA::paco

Definition at line 133 of file dt_constants.hh.

◆ PageBytes

const Addr gem5::MipsISA::PageBytes = 1ULL << PageShift

Definition at line 42 of file page_size.hh.

Referenced by gem5::MipsProcess::argsInit(), RoundPage(), gem5::MipsISA::MMU::translateFunctional(), and TruncPage().

◆ PageShift

const Addr gem5::MipsISA::PageShift = 13

Definition at line 41 of file page_size.hh.

Referenced by gem5::MipsISA::EmuLinux::EmuLinux().

◆ pc

Bitfield<4> gem5::MipsISA::pc

Definition at line 243 of file pra_constants.hh.

◆ pci

Bitfield<26> gem5::MipsISA::pci

Definition at line 182 of file pra_constants.hh.

◆ pcp

Bitfield<27> gem5::MipsISA::pcp

Definition at line 52 of file mt_constants.hh.

◆ pfn

Bitfield<29, 6> gem5::MipsISA::pfn

Definition at line 58 of file pra_constants.hh.

◆ procId

Bitfield<15, 8> gem5::MipsISA::procId

Definition at line 206 of file pra_constants.hh.

Referenced by gem5::MipsISA::ISA::configCP().

◆ pss

Bitfield<9, 6> gem5::MipsISA::pss

Definition at line 161 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> gem5::MipsISA::pState

Definition at line 322 of file pra_constants.hh.

◆ pTagLo

gem5::MipsISA::pTagLo

Definition at line 321 of file pra_constants.hh.

◆ ptc

Bitfield<7, 0> gem5::MipsISA::ptc

Definition at line 56 of file mt_constants.hh.

Referenced by gem5::ArmLinux32::archClone(), gem5::ArmLinux64::archClone(), gem5::ArmLinux::archClone(), gem5::PowerLinux::archClone(), gem5::RiscvLinux32::archClone(), gem5::RiscvLinux64::archClone(), gem5::SparcLinux::archClone(), and gem5::X86Linux::archClone().

◆ pteBase

gem5::MipsISA::pteBase

Definition at line 66 of file pra_constants.hh.

◆ ptlbe

Bitfield<25, 16> gem5::MipsISA::ptlbe

Definition at line 53 of file mt_constants.hh.

◆ pvpe

Bitfield<13, 10> gem5::MipsISA::pvpe

Definition at line 55 of file mt_constants.hh.

◆ px

Bitfield<23> gem5::MipsISA::px

Definition at line 116 of file pra_constants.hh.

Referenced by gem5::ArmISA::MMU::s1DirectPermBits64(), and gem5::ArmISA::MMU::s1IndirectPermBits64().

◆ r

Bitfield< 1 > gem5::MipsISA::r

Definition at line 98 of file pra_constants.hh.

Referenced by gem5::__to_number(), gem5::igbreg::Regs::MDIC::ADD_FIELD32(), gem5::ThermalModel::addReference(), gem5::ThermalModel::addResistor(), gem5::memory::DRAMInterface::allRanksDrained(), gem5::ruby::Set::AND(), Gem5SystemC::AtomicExtension::AtomicExtension(), gem5::AddrRangeMap< V, max_cache_size >::contains(), gem5::AddrRangeMap< V, max_cache_size >::contains(), gem5::AddrRangeMap< V, max_cache_size >::contains(), gem5::AddrRangeMap< V, max_cache_size >::contains(), gem5::ArmISA::decodeMrsMsrBankedIntRegIndex(), gem5::ArmISA::decodeMrsMsrBankedReg(), gem5::ruby::DirectoryMemory::DirectoryMemory(), gem5::PowerISA::IntArithOp::divide(), gem5::PowerISA::IntArithOp::divide(), gem5::loader::doGzipLoad(), gem5::memory::DRAMInterface::drainRanks(), EndBitUnion(), gem5::AddrRangeMap< V, max_cache_size >::find(), gem5::AddrRangeMap< V, max_cache_size >::find(), gem5::SparcISA::TlbMap::find(), gem5::statistics::Formula::Formula(), gem5::statistics::Formula::Formula(), gem5::ArmISA::fp64_sqrt(), gem5::Random::genRandom(), gem5::AMDGPUDevice::getAddrRanges(), gem5::ruby::RubyPort::PioResponsePort::getAddrRanges(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::getBackdoor(), gem5::memory::PhysicalMemory::getConfAddrRanges(), gem5::ruby::Sequencer::getHitTypeMachLatencyHist(), gem5::ruby::GPUCoalescer::getMissTypeMachLatencyHist(), gem5::ruby::Sequencer::getMissTypeMachLatencyHist(), gem5::GlobalSimLoopExitEvent::GlobalSimLoopExitEvent(), gem5::GlobalSimLoopExitEvent::GlobalSimLoopExitEvent(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::o3::LSQ::SplitDataRequest::initiateTranslation(), gem5::BaseCache::inRange(), gem5::AddrRangeMap< V, max_cache_size >::insert(), gem5::SparcISA::TlbMap::insert(), gem5::SparcISA::TlbMap::intersect(), gem5::ruby::Set::intersectionIsEmpty(), gem5::AddrRange::intersects(), gem5::AddrRangeMap< V, max_cache_size >::intersects(), gem5::AddrRangeMap< V, max_cache_size >::intersects(), gem5::VMA::intersects(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::invalidate_direct_mem_ptr(), gem5::memory::DRAMInterface::isBusy(), gem5::o3::LSQ::SplitDataRequest::isCacheBlockHit(), gem5::ruby::DirectoryMemory::isPresent(), gem5::VMA::isStrictSuperset(), gem5::AddrRange::isSubset(), gem5::VMA::isSubset(), gem5::ruby::Set::isSuperset(), gem5::LocalSimLoopExitEvent::LocalSimLoopExitEvent(), gem5::ruby::lookupTraceForAddress(), gem5::LupioBLK::lupioBLKRead(), gem5::LupioIPI::lupioIPIRead(), gem5::LupioPIC::lupioPicRead(), gem5::LupioRNG::lupioRNGRead(), gem5::LupioRTC::lupioRTCRead(), gem5::LupioTMR::lupioTMRRead(), sc_gem5::ScMainFiber::main(), gem5::ruby::DirectoryMemory::mapAddressToLocalIdx(), gem5::MemBackdoor::MemBackdoor(), gem5::MemBackdoorReq::MemBackdoorReq(), gem5::AddrRange::mergesWith(), gem5::VMA::mergesWith(), gem5::AddrRange::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::operator!=(), gem5::AddrRange::operator&(), gem5::PCEventQueue::MapCompare::operator()(), gem5::PCEventQueue::MapCompare::operator()(), gem5::statistics::operator*(), gem5::operator+(), gem5::statistics::operator+(), gem5::statistics::Formula::operator+=(), gem5::operator-(), gem5::statistics::operator-(), gem5::statistics::operator/(), gem5::statistics::Formula::operator/=(), gem5::AddrRange::operator<(), gem5::operator<(), gem5::operator<(), gem5::operator<=(), gem5::operator<=(), gem5::RefCountingPtr< MinorDynInst >::operator=(), gem5::RefCountingPtr< MinorDynInst >::operator=(), gem5::statistics::Formula::operator=(), gem5::AddrRange::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator==(), gem5::operator>(), gem5::operator>(), gem5::ruby::operator>(), gem5::operator>=(), gem5::operator>=(), gem5::ruby::Set::OR(), gem5::MathExpr::parse(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::Random::random(), gem5::MemBackdoor::range(), gem5::MemBackdoor::readable(), gem5::Iris::ThreadContext::readMem(), gem5::ArmISA::recipEstimate(), gem5::ArmISA::recipSqrtEstimate(), gem5::BaseXBar::recvRangeChange(), gem5::ruby::RubyPort::PioRequestPort::recvRangeChange(), gem5::RefCountingPtr< MinorDynInst >::RefCountingPtr(), gem5::RefCountingPtr< MinorDynInst >::RefCountingPtr(), gem5::RefCountingPtr< MinorDynInst >::RefCountingPtr(), sc_gem5::reportifyException(), gem5::branch_prediction::ReturnAddrStack::reset(), gem5::BaseSemihosting::retOK(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::MMU::s2PermBits64(), gem5::Cache::sendMSHRQueuePacket(), gem5::ArmISA::ISA::setMiscReg(), gem5::o3::LSQUnit::LSQEntry::setRequest(), gem5::memory::DRAMInterface::startup(), gem5::memory::DRAMInterface::suspend(), gem5::o3::LSQ::LSQRequest::taskId(), gem5::statistics::Formula::Temp, TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), RegisterBankTest::TestReg::TestReg(), gem5::LinearSystem::toStr(), gem5::MSHR::updateLockedRMWReadTarget(), gem5::VMA::VMA(), gem5::Iris::ThreadContext::writeMem(), and gem5::o3::LSQ::LSQRequest::~LSQRequest().

◆ r0

Bitfield<3> gem5::MipsISA::r0

Definition at line 139 of file pra_constants.hh.

Referenced by gem5::ArmISA::lsl128(), and gem5::ArmISA::lsr128().

◆ random

gem5::MipsISA::random

Definition at line 53 of file pra_constants.hh.

◆ re

Bitfield<25> gem5::MipsISA::re

Definition at line 114 of file pra_constants.hh.

◆ rev

Bitfield<7, 0> gem5::MipsISA::rev

Definition at line 207 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> gem5::MipsISA::ripl

Definition at line 187 of file pra_constants.hh.

◆ rnst

Bitfield<24, 23> gem5::MipsISA::rnst

Definition at line 87 of file mt_constants.hh.

◆ s

Bitfield< 2 > gem5::MipsISA::s

Definition at line 82 of file dt_constants.hh.

◆ sa

Bitfield<3, 0> gem5::MipsISA::sa

Definition at line 259 of file pra_constants.hh.

Referenced by dspExtr(), dspMulq(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), and dspShrl().

◆ scs

Bitfield<18> gem5::MipsISA::scs

Definition at line 70 of file mt_constants.hh.

Referenced by TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), and TEST_F().

◆ SIMD_LOG2N

const uint32_t gem5::MipsISA::SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }

Definition at line 105 of file dsp.hh.

Referenced by dspShll(), dspShra(), and dspShrl().

◆ SIMD_MAX_VALS

const uint32_t gem5::MipsISA::SIMD_MAX_VALS = 4

Definition at line 99 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ SIMD_NBITS

const uint32_t gem5::MipsISA::SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }

Definition at line 103 of file dsp.hh.

Referenced by dspMulq(), dspPrece(), dspPrecrqu(), signExtend(), simdPack(), and simdUnpack().

◆ SIMD_NVALS

const uint32_t gem5::MipsISA::SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }

Definition at line 101 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsaq(), dspPick(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), dspSubh(), simdPack(), and simdUnpack().

◆ sl

Bitfield<7, 4> gem5::MipsISA::sl

Definition at line 258 of file pra_constants.hh.

◆ sm

Bitfield<1> gem5::MipsISA::sm

Definition at line 273 of file pra_constants.hh.

◆ sp

Bitfield<4> gem5::MipsISA::sp

Definition at line 270 of file pra_constants.hh.

◆ sr

Bitfield<20> gem5::MipsISA::sr

Definition at line 119 of file pra_constants.hh.

Referenced by gem5::DistIface::SyncEvent::process().

◆ ss

Bitfield<11, 8> gem5::MipsISA::ss

Definition at line 257 of file pra_constants.hh.

◆ sst

Bitfield<8> gem5::MipsISA::sst

Definition at line 63 of file dt_constants.hh.

◆ ssv0

Bitfield<3, 0> gem5::MipsISA::ssv0

Definition at line 174 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> gem5::MipsISA::ssv1

Definition at line 173 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> gem5::MipsISA::ssv2

Definition at line 172 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> gem5::MipsISA::ssv3

Definition at line 171 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> gem5::MipsISA::ssv4

Definition at line 170 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> gem5::MipsISA::ssv5

Definition at line 169 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> gem5::MipsISA::ssv6

Definition at line 168 of file pra_constants.hh.

◆ ssv7

gem5::MipsISA::ssv7

Definition at line 167 of file pra_constants.hh.

◆ stlb

Bitfield<2> gem5::MipsISA::stlb

Definition at line 43 of file mt_constants.hh.

◆ su

Bitfield<15, 12> gem5::MipsISA::su

Definition at line 256 of file pra_constants.hh.

◆ sx

Bitfield<6> gem5::MipsISA::sx

Definition at line 135 of file pra_constants.hh.

◆ syp

Bitfield<2, 0> gem5::MipsISA::syp

Definition at line 102 of file dt_constants.hh.

◆ ta

Bitfield<19, 16> gem5::MipsISA::ta

Definition at line 255 of file pra_constants.hh.

Referenced by gem5::VegaISA::Walker::setBaseAddr().

◆ targTC

Bitfield<7, 0> gem5::MipsISA::targTC

Definition at line 63 of file mt_constants.hh.

◆ tb

Bitfield<27> gem5::MipsISA::tb

Definition at line 77 of file dt_constants.hh.

Referenced by gem5::DmaPort::DmaReqState::DmaReqState().

◆ tbe

Bitfield<17> gem5::MipsISA::tbe

Definition at line 80 of file mt_constants.hh.

Referenced by gem5::ruby::CHI::MN_TBETable::chooseNewDistributor(), and gem5::SparcISA::TLB::translateFunctional().

◆ tbi

Bitfield<4> gem5::MipsISA::tbi

Definition at line 100 of file dt_constants.hh.

◆ tbu

Bitfield<3> gem5::MipsISA::tbu

Definition at line 101 of file dt_constants.hh.

◆ tca

Bitfield<15> gem5::MipsISA::tca

Definition at line 54 of file mt_constants.hh.

◆ tcnum

Bitfield<19, 12> gem5::MipsISA::tcnum

Definition at line 97 of file dt_constants.hh.

◆ tcs

Bitfield<19> gem5::MipsISA::tcs

Definition at line 69 of file mt_constants.hh.

◆ tcu

gem5::MipsISA::tcu

Definition at line 85 of file mt_constants.hh.

◆ tcv

Bitfield<20> gem5::MipsISA::tcv

Definition at line 96 of file dt_constants.hh.

◆ tds

Bitfield<21> gem5::MipsISA::tds

Definition at line 88 of file mt_constants.hh.

◆ te

Bitfield<15> gem5::MipsISA::te

Definition at line 62 of file mt_constants.hh.

◆ tfcr

Bitfield<3> gem5::MipsISA::tfcr

Definition at line 87 of file dt_constants.hh.

◆ ti

Bitfield<30> gem5::MipsISA::ti

Definition at line 179 of file pra_constants.hh.

Referenced by gem5::ArmISA::DumpStats64::getTaskDetails(), gem5::ArmISA::DumpStats::getTaskDetails(), gem5::branch_prediction::SimpleIndirectPredictor::reset(), gem5::ArmISA::MMU::setTestInterface(), and gem5::ArmISA::TableWalker::setTestInterface().

◆ tim

Bitfield<1> gem5::MipsISA::tim

Definition at line 89 of file dt_constants.hh.

◆ tksu

Bitfield<12, 11> gem5::MipsISA::tksu

Definition at line 93 of file mt_constants.hh.

◆ tl

Bitfield< 0 > gem5::MipsISA::tl

Definition at line 254 of file pra_constants.hh.

Referenced by gem5::SparcISA::copyMiscRegs(), and gem5::SparcISA::SparcFaultBase::invoke().

◆ tlbs

Bitfield<29> gem5::MipsISA::tlbs

Definition at line 50 of file mt_constants.hh.

◆ tlsm

Bitfield<2> gem5::MipsISA::tlsm

Definition at line 88 of file dt_constants.hh.

◆ tmx

Bitfield<27> gem5::MipsISA::tmx

Definition at line 86 of file mt_constants.hh.

◆ ts

Bitfield< 27, 24 > gem5::MipsISA::ts

Definition at line 118 of file pra_constants.hh.

Referenced by EndBitUnion().

◆ tu

Bitfield<30, 28> gem5::MipsISA::tu

Definition at line 252 of file pra_constants.hh.

◆ tup

Bitfield<1> gem5::MipsISA::tup

Definition at line 132 of file dt_constants.hh.

Referenced by gem5::ruby::WeightBased::sortLinks().

◆ u

Bitfield< 3 > gem5::MipsISA::u

Definition at line 83 of file dt_constants.hh.

◆ um

Bitfield<4> gem5::MipsISA::um

Definition at line 138 of file pra_constants.hh.

◆ ut

Bitfield<30> gem5::MipsISA::ut

Definition at line 76 of file dt_constants.hh.

◆ ux

Bitfield<5> gem5::MipsISA::ux

Definition at line 136 of file pra_constants.hh.

Referenced by gem5::floorLog2(), gem5::ArmISA::MMU::s1DirectPermBits64(), and gem5::ArmISA::MMU::s1IndirectPermBits64().

◆ v

Bitfield<1> gem5::MipsISA::v

Definition at line 61 of file pra_constants.hh.

◆ vaddr

gem5::MipsISA::vaddr

Definition at line 278 of file pra_constants.hh.

◆ validModes

Bitfield<6, 5> gem5::MipsISA::validModes

Definition at line 99 of file dt_constants.hh.

◆ veic

Bitfield<6> gem5::MipsISA::veic

Definition at line 268 of file pra_constants.hh.

◆ vi

Bitfield<3> gem5::MipsISA::vi

Definition at line 228 of file pra_constants.hh.

◆ vint

Bitfield<5> gem5::MipsISA::vint

Definition at line 269 of file pra_constants.hh.

◆ vpa

Bitfield<0> gem5::MipsISA::vpa

Definition at line 74 of file mt_constants.hh.

◆ vpc

Bitfield<1> gem5::MipsISA::vpc

Definition at line 44 of file mt_constants.hh.

◆ vpn2

Bitfield<39, 13> gem5::MipsISA::vpn2

Definition at line 100 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> gem5::MipsISA::vpn2x

Definition at line 101 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> gem5::MipsISA::vs

Definition at line 149 of file pra_constants.hh.

◆ w

Bitfield< 30 > gem5::MipsISA::w

Definition at line 281 of file pra_constants.hh.

◆ wired

gem5::MipsISA::wired

Definition at line 89 of file pra_constants.hh.

◆ wp

Bitfield<22> gem5::MipsISA::wp

Definition at line 185 of file pra_constants.hh.

◆ wr

Bitfield<3> gem5::MipsISA::wr

Definition at line 244 of file pra_constants.hh.

Referenced by gem5::X86ISA::EndBitUnion().

◆ xtc

Bitfield<28, 21> gem5::MipsISA::xtc

Definition at line 68 of file mt_constants.hh.

Namespaces

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ ExtMachInst

◆ FaultVals

◆ FaultVect

◆ MachInst

◆ PCState

Enumeration Type Documentation

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ ConvertType

◆ ExcCode

◆ FCSRBits

◆ FCSRFields

◆ InterruptLevels

◆ RoundMode

Function Documentation

◆ addHalfLsb()

◆ bitrev()

◆ BitUnion32() [1/3]

◆ BitUnion32() [2/3]

◆ BitUnion32() [3/3]

◆ checkOverflow()

◆ dspAbs()

◆ dspAdd()

◆ dspAddh()

◆ dspCmp()

◆ dspCmpg()

◆ dspCmpgd()

◆ dspDpa()

◆ dspDpaq()

◆ dspDps()

◆ dspDpsq()

◆ dspExtp()

◆ dspExtpd()

◆ dspExtr()

◆ dspMaq()

◆ dspMul()

◆ dspMuleq()

◆ dspMuleu()

◆ dspMulq()

◆ dspMulsa()

◆ dspMulsaq()

◆ dspPack()

◆ dspPick()

◆ dspPrece()

◆ dspPrecrq()

◆ dspPrecrqu()

◆ dspPrecrSra()

◆ dspSaturate()

◆ dspShll()

◆ dspShra()

◆ dspShrl()

◆ dspSub()

◆ dspSubh()

◆ EndBitUnion() [1/35]

◆ EndBitUnion() [2/35]

◆ EndBitUnion() [3/35]

◆ EndBitUnion() [4/35]

◆ EndBitUnion() [5/35]

◆ EndBitUnion() [6/35]

◆ EndBitUnion() [7/35]

◆ EndBitUnion() [8/35]

◆ EndBitUnion() [9/35]

◆ EndBitUnion() [10/35]

◆ EndBitUnion() [11/35]

◆ EndBitUnion() [12/35]

◆ EndBitUnion() [13/35]

◆ EndBitUnion() [14/35]

◆ EndBitUnion() [15/35]