gem5 v25.0.0.1
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pcstate.hh File Reference
#include <iostream>
#include <memory>
#include <type_traits>
#include "base/compiler.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Classes

class  gem5::PCStateBase
class  gem5::GenericISA::PCStateWithNext
class  gem5::GenericISA::SimplePCState< InstWidth >
class  gem5::GenericISA::UPCState< InstWidth >
class  gem5::GenericISA::DelaySlotPCState< InstWidth >
class  gem5::GenericISA::DelaySlotUPCState< InstWidth >

Namespaces

namespace  gem5
 Copyright (c) 2024 Arm Limited All rights reserved.
namespace  gem5::GenericISA

Functions

static std::ostream & gem5::operator<< (std::ostream &os, const PCStateBase &pc)
static bool gem5::operator== (const PCStateBase &a, const PCStateBase &b)
static bool gem5::operator!= (const PCStateBase &a, const PCStateBase &b)

Generated on Sat Oct 18 2025 08:06:47 for gem5 by doxygen 1.14.0