int.hh File Reference

#include <string>
#include <vector>
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA
namespace	gem5::RiscvISA::int_reg

Enumerations

enum

: RegIndex {   gem5::RiscvISA::int_reg::_ZeroIdx , gem5::RiscvISA::int_reg::_RaIdx , gem5::RiscvISA::int_reg::_SpIdx , gem5::RiscvISA::int_reg::_GpIdx ,   gem5::RiscvISA::int_reg::_TpIdx , gem5::RiscvISA::int_reg::_T0Idx , gem5::RiscvISA::int_reg::_T1Idx , gem5::RiscvISA::int_reg::_T2Idx ,   gem5::RiscvISA::int_reg::_S0Idx , gem5::RiscvISA::int_reg::_S1Idx , gem5::RiscvISA::int_reg::_A0Idx , gem5::RiscvISA::int_reg::_A1Idx ,   gem5::RiscvISA::int_reg::_A2Idx , gem5::RiscvISA::int_reg::_A3Idx , gem5::RiscvISA::int_reg::_A4Idx , gem5::RiscvISA::int_reg::_A5Idx ,   gem5::RiscvISA::int_reg::_A6Idx , gem5::RiscvISA::int_reg::_A7Idx , gem5::RiscvISA::int_reg::_S2Idx , gem5::RiscvISA::int_reg::_S3Idx ,   gem5::RiscvISA::int_reg::_S4Idx , gem5::RiscvISA::int_reg::_S5Idx , gem5::RiscvISA::int_reg::_S6Idx , gem5::RiscvISA::int_reg::_S7Idx ,   gem5::RiscvISA::int_reg::_S8Idx , gem5::RiscvISA::int_reg::_S9Idx , gem5::RiscvISA::int_reg::_S10Idx , gem5::RiscvISA::int_reg::_S11Idx ,   gem5::RiscvISA::int_reg::_T3Idx , gem5::RiscvISA::int_reg::_T4Idx , gem5::RiscvISA::int_reg::_T5Idx , gem5::RiscvISA::int_reg::_T6Idx ,   gem5::RiscvISA::int_reg::NumArchRegs , gem5::RiscvISA::int_reg::_Ureg0Idx = NumArchRegs , gem5::RiscvISA::int_reg::NumRegs }

Functions
constexpr RegClass	gem5::RiscvISA::intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)

Variables
constexpr RegId	gem5::RiscvISA::int_reg::Zero = intRegClass[_ZeroIdx]
constexpr RegId	gem5::RiscvISA::int_reg::Ra = intRegClass[_RaIdx]
constexpr RegId	gem5::RiscvISA::int_reg::Sp = intRegClass[_SpIdx]
constexpr RegId	gem5::RiscvISA::int_reg::Gp = intRegClass[_GpIdx]
constexpr RegId	gem5::RiscvISA::int_reg::Tp = intRegClass[_TpIdx]
constexpr RegId	gem5::RiscvISA::int_reg::T0 = intRegClass[_T0Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T1 = intRegClass[_T1Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T2 = intRegClass[_T2Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S0 = intRegClass[_S0Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S1 = intRegClass[_S1Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A0 = intRegClass[_A0Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A1 = intRegClass[_A1Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A2 = intRegClass[_A2Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A3 = intRegClass[_A3Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A4 = intRegClass[_A4Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A5 = intRegClass[_A5Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A6 = intRegClass[_A6Idx]
constexpr RegId	gem5::RiscvISA::int_reg::A7 = intRegClass[_A7Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S2 = intRegClass[_S2Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S3 = intRegClass[_S3Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S4 = intRegClass[_S4Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S5 = intRegClass[_S5Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S6 = intRegClass[_S6Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S7 = intRegClass[_S7Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S8 = intRegClass[_S8Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S9 = intRegClass[_S9Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S10 = intRegClass[_S10Idx]
constexpr RegId	gem5::RiscvISA::int_reg::S11 = intRegClass[_S11Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T3 = intRegClass[_T3Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T4 = intRegClass[_T4Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T5 = intRegClass[_T5Idx]
constexpr RegId	gem5::RiscvISA::int_reg::T6 = intRegClass[_T6Idx]
constexpr RegId	gem5::RiscvISA::int_reg::Ureg0 = intRegClass[_Ureg0Idx]
const std::vector< std::string >	gem5::RiscvISA::int_reg::RegNames
constexpr auto &	gem5::RiscvISA::ReturnAddrReg = int_reg::Ra
constexpr auto &	gem5::RiscvISA::StackPointerReg = int_reg::Sp
constexpr auto &	gem5::RiscvISA::ThreadPointerReg = int_reg::Tp
constexpr auto &	gem5::RiscvISA::ReturnValueReg = int_reg::A0
constexpr auto &	gem5::RiscvISA::AMOTempReg = int_reg::Ureg0
constexpr auto &	gem5::RiscvISA::SyscallNumReg = int_reg::A7
constexpr RegId	gem5::RiscvISA::ArgumentRegs []
const std::vector< RegId >	gem5::RiscvISA::PushPopRegList
constexpr RegId	gem5::RiscvISA::StackRegs []