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gem5
v19.0.0.0
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#include "arch/alpha/generated/max_inst_regs.hh"#include "arch/alpha/ipr.hh"#include "arch/generic/types.hh"#include "arch/generic/vec_pred_reg.hh"#include "arch/generic/vec_reg.hh"#include "base/types.hh"Go to the source code of this file.
Namespaces | |
| AlphaISA | |
Typedefs | |
| using | AlphaISA::VecElem = ::DummyVecElem |
| using | AlphaISA::VecReg = ::DummyVecReg |
| using | AlphaISA::ConstVecReg = ::DummyConstVecReg |
| using | AlphaISA::VecRegContainer = ::DummyVecRegContainer |
| using | AlphaISA::VecPredReg = ::DummyVecPredReg |
| using | AlphaISA::ConstVecPredReg = ::DummyConstVecPredReg |
| using | AlphaISA::VecPredRegContainer = ::DummyVecPredRegContainer |
Enumerations | |
| enum | AlphaISA::MiscRegIndex { AlphaISA::MISCREG_FPCR = NumInternalProcRegs, AlphaISA::MISCREG_UNIQ, AlphaISA::MISCREG_LOCKFLAG, AlphaISA::MISCREG_LOCKADDR, AlphaISA::MISCREG_INTR, AlphaISA::NUM_MISCREGS } |