AlphaISA Namespace Reference

Namespaces
	Kernel

Classes
class	AlignmentFault
class	AlphaFault
class	AlphaLinuxProcess
	A process with emulated Alpha/Linux syscalls. More...
struct	AlphaRequestFlags
	Alpha-specific memory request flags. More...
class	ArithmeticFault
class	Decoder
class	DtbAcvFault
class	DtbAlignmentFault
class	DtbFault
class	DtbPageFault
class	FloatEnableFault
class	IntegerOverflowFault
class	InterruptFault
class	Interrupts
class	ISA
class	ItbAcvFault
class	ItbFault
class	ItbPageFault
class	MachineCheckFault
class	NDtbMissFault
struct	PageTableEntry
class	PalFault
class	PDtbMissFault
class	ProcessInfo
class	RemoteGDB
class	ResetFault
class	StackTrace
class	TLB
struct	TlbEntry
class	UnimplementedOpcodeFault
struct	VAddr
class	VectorEnableFault

Typedefs
typedef Addr	FaultVect
using	VecElem = ::DummyVecElem
using	VecReg = ::DummyVecReg
using	ConstVecReg = ::DummyConstVecReg
using	VecRegContainer = ::DummyVecRegContainer
using	VecPredReg = ::DummyVecPredReg
using	ConstVecPredReg = ::DummyConstVecPredReg
using	VecPredRegContainer = ::DummyVecPredRegContainer
typedef uint32_t	MachInst
typedef uint64_t	ExtMachInst
typedef GenericISA::SimplePCState< MachInst >	PCState

Enumerations
enum	md_ipr_names {   RAW_IPR_ISR = 0x100, RAW_IPR_ITB_TAG = 0x101, RAW_IPR_ITB_PTE = 0x102, RAW_IPR_ITB_ASN = 0x103,   RAW_IPR_ITB_PTE_TEMP = 0x104, RAW_IPR_ITB_IA = 0x105, RAW_IPR_ITB_IAP = 0x106, RAW_IPR_ITB_IS = 0x107,   RAW_IPR_SIRR = 0x108, RAW_IPR_ASTRR = 0x109, RAW_IPR_ASTER = 0x10a, RAW_IPR_EXC_ADDR = 0x10b,   RAW_IPR_EXC_SUM = 0x10c, RAW_IPR_EXC_MASK = 0x10d, RAW_IPR_PAL_BASE = 0x10e, RAW_IPR_ICM = 0x10f,   RAW_IPR_IPLR = 0x110, RAW_IPR_INTID = 0x111, RAW_IPR_IFAULT_VA_FORM = 0x112, RAW_IPR_IVPTBR = 0x113,   RAW_IPR_HWINT_CLR = 0x115, RAW_IPR_SL_XMIT = 0x116, RAW_IPR_SL_RCV = 0x117, RAW_IPR_ICSR = 0x118,   RAW_IPR_IC_FLUSH = 0x119, RAW_IPR_IC_PERR_STAT = 0x11a, RAW_IPR_PMCTR = 0x11c, RAW_IPR_PALtemp0 = 0x140,   RAW_IPR_PALtemp1 = 0x141, RAW_IPR_PALtemp2 = 0x142, RAW_IPR_PALtemp3 = 0x143, RAW_IPR_PALtemp4 = 0x144,   RAW_IPR_PALtemp5 = 0x145, RAW_IPR_PALtemp6 = 0x146, RAW_IPR_PALtemp7 = 0x147, RAW_IPR_PALtemp8 = 0x148,   RAW_IPR_PALtemp9 = 0x149, RAW_IPR_PALtemp10 = 0x14a, RAW_IPR_PALtemp11 = 0x14b, RAW_IPR_PALtemp12 = 0x14c,   RAW_IPR_PALtemp13 = 0x14d, RAW_IPR_PALtemp14 = 0x14e, RAW_IPR_PALtemp15 = 0x14f, RAW_IPR_PALtemp16 = 0x150,   RAW_IPR_PALtemp17 = 0x151, RAW_IPR_PALtemp18 = 0x152, RAW_IPR_PALtemp19 = 0x153, RAW_IPR_PALtemp20 = 0x154,   RAW_IPR_PALtemp21 = 0x155, RAW_IPR_PALtemp22 = 0x156, RAW_IPR_PALtemp23 = 0x157, RAW_IPR_DTB_ASN = 0x200,   RAW_IPR_DTB_CM = 0x201, RAW_IPR_DTB_TAG = 0x202, RAW_IPR_DTB_PTE = 0x203, RAW_IPR_DTB_PTE_TEMP = 0x204,   RAW_IPR_MM_STAT = 0x205, RAW_IPR_VA = 0x206, RAW_IPR_VA_FORM = 0x207, RAW_IPR_MVPTBR = 0x208,   RAW_IPR_DTB_IAP = 0x209, RAW_IPR_DTB_IA = 0x20a, RAW_IPR_DTB_IS = 0x20b, RAW_IPR_ALT_MODE = 0x20c,   RAW_IPR_CC = 0x20d, RAW_IPR_CC_CTL = 0x20e, RAW_IPR_MCSR = 0x20f, RAW_IPR_DC_FLUSH = 0x210,   RAW_IPR_DC_PERR_STAT = 0x212, RAW_IPR_DC_TEST_CTL = 0x213, RAW_IPR_DC_TEST_TAG = 0x214, RAW_IPR_DC_TEST_TAG_TEMP = 0x215,   RAW_IPR_DC_MODE = 0x216, RAW_IPR_MAF_MODE = 0x217, MaxInternalProcRegs }
enum	MiscRegIpr {   MinWriteOnlyIpr, IPR_HWINT_CLR = MinWriteOnlyIpr, IPR_SL_XMIT, IPR_DC_FLUSH,   IPR_IC_FLUSH, IPR_ALT_MODE, IPR_DTB_IA, IPR_DTB_IAP,   IPR_ITB_IA, MaxWriteOnlyIpr, IPR_ITB_IAP = MaxWriteOnlyIpr, MinReadOnlyIpr,   IPR_INTID = MinReadOnlyIpr, IPR_SL_RCV, IPR_MM_STAT, IPR_ITB_PTE_TEMP,   MaxReadOnlyIpr, IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, IPR_ISR, IPR_ITB_TAG,   IPR_ITB_PTE, IPR_ITB_ASN, IPR_ITB_IS, IPR_SIRR,   IPR_ASTRR, IPR_ASTER, IPR_EXC_ADDR, IPR_EXC_SUM,   IPR_EXC_MASK, IPR_PAL_BASE, IPR_ICM, IPR_IPLR,   IPR_IFAULT_VA_FORM, IPR_IVPTBR, IPR_ICSR, IPR_IC_PERR_STAT,   IPR_PMCTR, IPR_PALtemp0, IPR_PALtemp1, IPR_PALtemp2,   IPR_PALtemp3, IPR_PALtemp4, IPR_PALtemp5, IPR_PALtemp6,   IPR_PALtemp7, IPR_PALtemp8, IPR_PALtemp9, IPR_PALtemp10,   IPR_PALtemp11, IPR_PALtemp12, IPR_PALtemp13, IPR_PALtemp14,   IPR_PALtemp15, IPR_PALtemp16, IPR_PALtemp17, IPR_PALtemp18,   IPR_PALtemp19, IPR_PALtemp20, IPR_PALtemp21, IPR_PALtemp22,   IPR_PALtemp23, IPR_DTB_ASN, IPR_DTB_CM, IPR_DTB_TAG,   IPR_DTB_PTE, IPR_VA, IPR_VA_FORM, IPR_MVPTBR,   IPR_DTB_IS, IPR_CC, IPR_CC_CTL, IPR_MCSR,   IPR_DC_PERR_STAT, IPR_DC_TEST_CTL, IPR_DC_TEST_TAG, IPR_DC_TEST_TAG_TEMP,   IPR_DC_MODE, IPR_MAF_MODE, NumInternalProcRegs }
enum	InterruptLevels {   INTLEVEL_SOFTWARE_MIN = 4, INTLEVEL_SOFTWARE_MAX = 19, INTLEVEL_EXTERNAL_MIN = 20, INTLEVEL_EXTERNAL_MAX = 34,   INTLEVEL_IRQ0 = 20, INTLEVEL_IRQ1 = 21, INTINDEX_ETHERNET = 0, INTINDEX_SCSI = 1,   INTLEVEL_IRQ2 = 22, INTLEVEL_IRQ3 = 23, INTLEVEL_SERIAL = 33, NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }
enum	mode_type {   mode_kernel = 0, mode_executive = 1, mode_supervisor = 2, mode_user = 3,   mode_number }
enum	MiscRegIndex {   MISCREG_FPCR = NumInternalProcRegs, MISCREG_UNIQ, MISCREG_LOCKFLAG, MISCREG_LOCKADDR,   MISCREG_INTR, NUM_MISCREGS }
enum	annotes { ANNOTE_NONE = 0, ITOUCH_ANNOTE = 0xffffffff }

Functions
template<typename T >
TLB *	getITBPtr (T *tc)
template<typename T >
TLB *	getDTBPtr (T *tc)
void	initIPRs (ThreadContext *tc, int cpuId)
void	copyIprs (ThreadContext *src, ThreadContext *dest)
Addr	VAddrImpl (Addr a)
Addr	VAddrVPN (Addr a)
Addr	VAddrOffset (Addr a)
Addr	VAddrSpaceEV5 (Addr a)
Addr	VAddrSpaceEV6 (Addr a)
bool	PAddrIprSpace (Addr a)
Addr	Phys2K0Seg (Addr addr)
int	DTB_ASN_ASN (uint64_t reg)
Addr	DTB_PTE_PPN (uint64_t reg)
int	DTB_PTE_XRE (uint64_t reg)
int	DTB_PTE_XWE (uint64_t reg)
int	DTB_PTE_FONR (uint64_t reg)
int	DTB_PTE_FONW (uint64_t reg)
int	DTB_PTE_GH (uint64_t reg)
int	DTB_PTE_ASMA (uint64_t reg)
int	ITB_ASN_ASN (uint64_t reg)
Addr	ITB_PTE_PPN (uint64_t reg)
int	ITB_PTE_XRE (uint64_t reg)
bool	ITB_PTE_FONR (uint64_t reg)
bool	ITB_PTE_FONW (uint64_t reg)
int	ITB_PTE_GH (uint64_t reg)
bool	ITB_PTE_ASMA (uint64_t reg)
uint64_t	MCSR_SP (uint64_t reg)
bool	ICSR_SDE (uint64_t reg)
int	ICSR_SPE (uint64_t reg)
bool	ICSR_FPE (uint64_t reg)
uint64_t	ALT_MODE_AM (uint64_t reg)
uint64_t	DTB_CM_CM (uint64_t reg)
uint64_t	ICM_CM (uint64_t reg)
int	Opcode (MachInst inst)
int	Ra (MachInst inst)
void	initializeIprTable ()
bool	IprIsWritable (int index)
bool	IprIsReadable (int index)
StaticInstPtr	decodeInst (ExtMachInst)
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
void	handleLockedRead (XC *xc, const RequestPtr &req)
template<class XC >
void	handleLockedSnoopHit (XC *xc)
template<class XC >
bool	handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
template<class XC >
void	globalClearExclusive (XC *xc)
Cycles	handleIprRead (ThreadContext *, Packet *)
Cycles	handleIprWrite (ThreadContext *, Packet *)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	copyRegs (ThreadContext *src, ThreadContext *dest)
void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void	skipFunction (ThreadContext *tc)
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
bool	inUserMode (ThreadContext *tc)
bool	PcPAL (Addr addr)
Addr	PteAddr (Addr a)
bool	IsUSeg (Addr a)
bool	IsK0Seg (Addr a)
Addr	K0Seg2Phys (Addr addr)
bool	IsK1Seg (Addr a)
Addr	TruncPage (Addr addr)
Addr	RoundPage (Addr addr)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
uint64_t	getExecutingAsid (ThreadContext *tc)
PageTableEntry	kernel_pte_lookup (PortProxy &mem, Addr ptbr, VAddr vaddr)
Addr	vtophys (Addr vaddr)
Addr	vtophys (ThreadContext *tc, Addr addr)

Variables
int	break_ipl = -1
const uint64_t	AsnMask = ULL(0xff)
const int	VAddrImplBits = 43
const Addr	VAddrImplMask = (ULL(1) << VAddrImplBits) - 1
const Addr	VAddrUnImplMask = ~VAddrImplMask
const int	PAddrImplBits = 44
const Addr	PAddrImplMask = (ULL(1) << PAddrImplBits) - 1
const Addr	PAddrUncachedBit39 = ULL(0x8000000000)
const Addr	PAddrUncachedBit40 = ULL(0x10000000000)
const Addr	PAddrUncachedBit43 = ULL(0x80000000000)
const Addr	PAddrUncachedMask = ULL(0x807ffffffff)
const uint64_t	MM_STAT_BAD_VA_MASK = ULL(0x0020)
const uint64_t	MM_STAT_DTB_MISS_MASK = ULL(0x0010)
const uint64_t	MM_STAT_FONW_MASK = ULL(0x0008)
const uint64_t	MM_STAT_FONR_MASK = ULL(0x0004)
const uint64_t	MM_STAT_ACV_MASK = ULL(0x0002)
const uint64_t	MM_STAT_WR_MASK = ULL(0x0001)
const Addr	PalBase = 0x4000
const Addr	PalMax = 0x10000
md_ipr_names	MiscRegIndexToIpr [NumInternalProcRegs]
int	IprToMiscRegIndex [MaxInternalProcRegs]
const ByteOrder	GuestByteOrder = LittleEndianByteOrder
const Addr	PageShift = 13
const Addr	PageBytes = ULL(1) << PageShift
const Addr	PageMask = ~(PageBytes - 1)
const Addr	PageOffset = PageBytes - 1
const Addr	PteShift = 3
const Addr	NPtePageShift = PageShift - PteShift
const Addr	NPtePage = ULL(1) << NPtePageShift
const Addr	PteMask = NPtePage - 1
const Addr	USegBase = ULL(0x0)
const Addr	USegEnd = ULL(0x000003ffffffffff)
const Addr	K0SegBase = ULL(0xfffffc0000000000)
const Addr	K0SegEnd = ULL(0xfffffdffffffffff)
const Addr	K1SegBase = ULL(0xfffffe0000000000)
const Addr	K1SegEnd = ULL(0xffffffffffffffff)
const int	MachineBytes = 8
const bool	HasUnalignedMemAcc = false
const bool	CurThreadInfoImplemented = true
const int	CurThreadInfoReg = AlphaISA::IPR_PALtemp23
const int	MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1
constexpr unsigned	NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
constexpr size_t	VecRegSizeBytes = ::DummyVecRegSizeBytes
constexpr size_t	VecPredRegSizeBits = ::DummyVecPredRegSizeBits
constexpr bool	VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
const RegIndex	ZeroReg = 31
const RegIndex	StackPointerReg = 30
const RegIndex	GlobalPointerReg = 29
const RegIndex	ProcedureValueReg = 27
const RegIndex	ReturnAddressReg = 26
const RegIndex	ReturnValueReg = 0
const RegIndex	FramePointerReg = 15
const RegIndex	SyscallNumReg = 0
const RegIndex	FirstArgumentReg = 16
const RegIndex	SyscallPseudoReturnReg = 20
const RegIndex	SyscallSuccessReg = 19
const int	NumIntArchRegs = 32
const int	NumPALShadowRegs = 8
const int	NumFloatArchRegs = 32
const int	NumIntRegs = NumIntArchRegs + NumPALShadowRegs
const int	NumFloatRegs = NumFloatArchRegs
const int	NumVecRegs = 1
const int	NumVecPredRegs = 1
const int	NumCCRegs = 0
const int	NumMiscRegs = NUM_MISCREGS
const int	TotalNumRegs
const int	reg_redir [NumIntRegs]

Typedef Documentation

ConstVecPredReg

using AlphaISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 59 of file registers.hh.

ConstVecReg

using AlphaISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 52 of file registers.hh.

ExtMachInst

typedef uint64_t AlphaISA::ExtMachInst

Definition at line 41 of file types.hh.

FaultVect

typedef Addr AlphaISA::FaultVect

Definition at line 43 of file faults.hh.

MachInst

typedef uint32_t AlphaISA::MachInst

Definition at line 40 of file types.hh.

PCState

typedef GenericISA::SimplePCState<MachInst> AlphaISA::PCState

Definition at line 43 of file types.hh.

VecElem

using AlphaISA::VecElem = typedef ::DummyVecElem

Definition at line 50 of file registers.hh.

VecPredReg

using AlphaISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 58 of file registers.hh.

VecPredRegContainer

using AlphaISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 60 of file registers.hh.

VecReg

using AlphaISA::VecReg = typedef ::DummyVecReg

Definition at line 51 of file registers.hh.

VecRegContainer

using AlphaISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 53 of file registers.hh.

Enumeration Type Documentation

annotes

enum AlphaISA::annotes

Enumerator
ANNOTE_NONE
ITOUCH_ANNOTE

Definition at line 45 of file types.hh.

InterruptLevels

enum AlphaISA::InterruptLevels

Enumerator
INTLEVEL_SOFTWARE_MIN
INTLEVEL_SOFTWARE_MAX
INTLEVEL_EXTERNAL_MIN
INTLEVEL_EXTERNAL_MAX
INTLEVEL_IRQ0
INTLEVEL_IRQ1
INTINDEX_ETHERNET
INTINDEX_SCSI
INTLEVEL_IRQ2
INTLEVEL_IRQ3
INTLEVEL_SERIAL
NumInterruptLevels

Definition at line 77 of file isa_traits.hh.

md_ipr_names

enum AlphaISA::md_ipr_names

Enumerator
RAW_IPR_ISR
RAW_IPR_ITB_TAG
RAW_IPR_ITB_PTE
RAW_IPR_ITB_ASN
RAW_IPR_ITB_PTE_TEMP
RAW_IPR_ITB_IA
RAW_IPR_ITB_IAP
RAW_IPR_ITB_IS
RAW_IPR_SIRR
RAW_IPR_ASTRR
RAW_IPR_ASTER
RAW_IPR_EXC_ADDR
RAW_IPR_EXC_SUM
RAW_IPR_EXC_MASK
RAW_IPR_PAL_BASE
RAW_IPR_ICM
RAW_IPR_IPLR
RAW_IPR_INTID
RAW_IPR_IFAULT_VA_FORM
RAW_IPR_IVPTBR
RAW_IPR_HWINT_CLR
RAW_IPR_SL_XMIT
RAW_IPR_SL_RCV
RAW_IPR_ICSR
RAW_IPR_IC_FLUSH
RAW_IPR_IC_PERR_STAT
RAW_IPR_PMCTR
RAW_IPR_PALtemp0
RAW_IPR_PALtemp1
RAW_IPR_PALtemp2
RAW_IPR_PALtemp3
RAW_IPR_PALtemp4
RAW_IPR_PALtemp5
RAW_IPR_PALtemp6
RAW_IPR_PALtemp7
RAW_IPR_PALtemp8
RAW_IPR_PALtemp9
RAW_IPR_PALtemp10
RAW_IPR_PALtemp11
RAW_IPR_PALtemp12
RAW_IPR_PALtemp13
RAW_IPR_PALtemp14
RAW_IPR_PALtemp15
RAW_IPR_PALtemp16
RAW_IPR_PALtemp17
RAW_IPR_PALtemp18
RAW_IPR_PALtemp19
RAW_IPR_PALtemp20
RAW_IPR_PALtemp21
RAW_IPR_PALtemp22
RAW_IPR_PALtemp23
RAW_IPR_DTB_ASN
RAW_IPR_DTB_CM
RAW_IPR_DTB_TAG
RAW_IPR_DTB_PTE
RAW_IPR_DTB_PTE_TEMP
RAW_IPR_MM_STAT
RAW_IPR_VA
RAW_IPR_VA_FORM
RAW_IPR_MVPTBR
RAW_IPR_DTB_IAP
RAW_IPR_DTB_IA
RAW_IPR_DTB_IS
RAW_IPR_ALT_MODE
RAW_IPR_CC
RAW_IPR_CC_CTL
RAW_IPR_MCSR
RAW_IPR_DC_FLUSH
RAW_IPR_DC_PERR_STAT
RAW_IPR_DC_TEST_CTL
RAW_IPR_DC_TEST_TAG
RAW_IPR_DC_TEST_TAG_TEMP
RAW_IPR_DC_MODE
RAW_IPR_MAF_MODE
MaxInternalProcRegs

Definition at line 41 of file ipr.hh.

MiscRegIndex

enum AlphaISA::MiscRegIndex

Enumerator
MISCREG_FPCR
MISCREG_UNIQ
MISCREG_LOCKFLAG
MISCREG_LOCKADDR
MISCREG_INTR
NUM_MISCREGS

Definition at line 64 of file registers.hh.

MiscRegIpr

enum AlphaISA::MiscRegIpr

Enumerator
MinWriteOnlyIpr
IPR_HWINT_CLR
IPR_SL_XMIT
IPR_DC_FLUSH
IPR_IC_FLUSH
IPR_ALT_MODE
IPR_DTB_IA
IPR_DTB_IAP
IPR_ITB_IA
MaxWriteOnlyIpr
IPR_ITB_IAP
MinReadOnlyIpr
IPR_INTID
IPR_SL_RCV
IPR_MM_STAT
IPR_ITB_PTE_TEMP
MaxReadOnlyIpr
IPR_DTB_PTE_TEMP
IPR_ISR
IPR_ITB_TAG
IPR_ITB_PTE
IPR_ITB_ASN
IPR_ITB_IS
IPR_SIRR
IPR_ASTRR
IPR_ASTER
IPR_EXC_ADDR
IPR_EXC_SUM
IPR_EXC_MASK
IPR_PAL_BASE
IPR_ICM
IPR_IPLR
IPR_IFAULT_VA_FORM
IPR_IVPTBR
IPR_ICSR
IPR_IC_PERR_STAT
IPR_PMCTR
IPR_PALtemp0
IPR_PALtemp1
IPR_PALtemp2
IPR_PALtemp3
IPR_PALtemp4
IPR_PALtemp5
IPR_PALtemp6
IPR_PALtemp7
IPR_PALtemp8
IPR_PALtemp9
IPR_PALtemp10
IPR_PALtemp11
IPR_PALtemp12
IPR_PALtemp13
IPR_PALtemp14
IPR_PALtemp15
IPR_PALtemp16
IPR_PALtemp17
IPR_PALtemp18
IPR_PALtemp19
IPR_PALtemp20
IPR_PALtemp21
IPR_PALtemp22
IPR_PALtemp23
IPR_DTB_ASN
IPR_DTB_CM
IPR_DTB_TAG
IPR_DTB_PTE
IPR_VA
IPR_VA_FORM
IPR_MVPTBR
IPR_DTB_IS
IPR_CC
IPR_CC_CTL
IPR_MCSR
IPR_DC_PERR_STAT
IPR_DC_TEST_CTL
IPR_DC_TEST_TAG
IPR_DC_TEST_TAG_TEMP
IPR_DC_MODE
IPR_MAF_MODE
NumInternalProcRegs

Definition at line 126 of file ipr.hh.

mode_type

enum AlphaISA::mode_type

Enumerator
mode_kernel
mode_executive
mode_supervisor
mode_user
mode_number

Definition at line 98 of file isa_traits.hh.

Function Documentation

advancePC()

void AlphaISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 98 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::advance().

Referenced by BaseSimpleCPU::advancePC(), Checker< O3CPUImpl >::advancePC(), Checker< O3CPUImpl >::Checker(), DefaultCommit< Impl >::commitInsts(), StaticInst::completeAcc(), Minor::Fetch2::evaluate(), DefaultFetch< Impl >::lookupAndUpdateNextPC(), BaseDynInst< Impl >::mispredicted(), BPredUnit::predict(), DefaultIEW< Impl >::squashDueToBranch(), Minor::Execute::tryToBranch(), Checker< O3CPUImpl >::validateState(), and Checker< O3CPUImpl >::verify().

ALT_MODE_AM()

uint64_t AlphaISA::ALT_MODE_AM ( uint64_t  reg )

inline

Definition at line 95 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

buildRetPC()

PCState AlphaISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 46 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::advance(), ArmISA::fp, and getArgument().

Referenced by BPredUnit::predict().

copyIprs()

void AlphaISA::copyIprs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 448 of file ev5.cc.

References ArmISA::i, NumInternalProcRegs, ThreadContext::readMiscRegNoEffect(), and ThreadContext::setMiscRegNoEffect().

Referenced by copyMiscRegs().

copyMiscRegs()

void AlphaISA::copyMiscRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 86 of file utility.cc.

References copyIprs(), MISCREG_FPCR, MISCREG_LOCKADDR, MISCREG_LOCKFLAG, MISCREG_UNIQ, ThreadContext::readMiscRegNoEffect(), and ThreadContext::setMiscRegNoEffect().

Referenced by AlphaLinux::archClone(), copyRegs(), and RoundPage().

copyRegs()

void AlphaISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 65 of file utility.cc.

References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readFloatReg(), ThreadContext::readIntReg(), ThreadContext::setFloatReg(), and ThreadContext::setIntReg().

Referenced by O3ThreadContext< Impl >::copyArchRegs(), SimpleThread::copyArchRegs(), and RoundPage().

decodeInst()

StaticInstPtr AlphaISA::decodeInst

(

ExtMachInst

)

DTB_ASN_ASN()

int AlphaISA::DTB_ASN_ASN ( uint64_t  reg )

inline

Definition at line 70 of file ev5.hh.

References AsnMask.

Referenced by getExecutingAsid(), AlphaISA::ISA::setIpr(), AlphaISA::TLB::translateData(), and AlphaISA::TLB::translateInst().

DTB_CM_CM()

uint64_t AlphaISA::DTB_CM_CM ( uint64_t  reg )

inline

Definition at line 96 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

DTB_PTE_ASMA()

int AlphaISA::DTB_PTE_ASMA ( uint64_t  reg )

inline

Definition at line 78 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_FONR()

int AlphaISA::DTB_PTE_FONR ( uint64_t  reg )

inline

Definition at line 75 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_FONW()

int AlphaISA::DTB_PTE_FONW ( uint64_t  reg )

inline

Definition at line 76 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_GH()

int AlphaISA::DTB_PTE_GH ( uint64_t  reg )

inline

Definition at line 77 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_PPN()

Addr AlphaISA::DTB_PTE_PPN ( uint64_t  reg )

inline

Definition at line 71 of file ev5.hh.

References PageShift, and ULL.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_XRE()

int AlphaISA::DTB_PTE_XRE ( uint64_t  reg )

inline

Definition at line 73 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

DTB_PTE_XWE()

int AlphaISA::DTB_PTE_XWE ( uint64_t  reg )

inline

Definition at line 74 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

getArgument()

uint64_t AlphaISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 41 of file utility.cc.

References FullSystem, ThreadContext::getVirtProxy(), ArmISA::NumArgumentRegs, panic, PortProxy::read(), ThreadContext::readFloatReg(), ThreadContext::readIntReg(), ArmISA::sp, and StackPointerReg.

Referenced by buildRetPC(), GuestABI::Argument< PseudoInstABI, uint64_t >::get(), Arguments::getArg(), FreeBSD::UDelayEvent::process(), and Linux::UDelayEvent::process().

getDTBPtr()

template<typename T >

TLB* AlphaISA::getDTBPtr

(

T *

tc

)

Definition at line 57 of file ev5.cc.

References ArmISA::tlb.

Referenced by AlphaISA::ISA::readIpr(), AlphaISA::ISA::setIpr(), and ThreadContext::~ThreadContext().

getExecutingAsid()

uint64_t AlphaISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 104 of file utility.hh.

References DTB_ASN_ASN(), IPR_DTB_ASN, and ThreadContext::readMiscRegNoEffect().

Referenced by Trace::ExeTracerRecord::traceInst().

getITBPtr()

template<typename T >

TLB* AlphaISA::getITBPtr

(

T *

tc

)

Definition at line 48 of file ev5.cc.

References ArmISA::tlb.

Referenced by AlphaISA::ISA::setIpr(), and ThreadContext::~ThreadContext().

globalClearExclusive()

template<class XC >

void AlphaISA::globalClearExclusive ( XC *  xc )

inline

Definition at line 140 of file locked_mem.hh.

handleIprRead()

Cycles AlphaISA::handleIprRead ( ThreadContext *  , Packet *    )

inline

Definition at line 48 of file mmapped_ipr.hh.

Referenced by AtomicSimpleCPU::amoMem(), BaseKvmCPU::doMMIOAccess(), LSQ< Impl >::SingleDataRequest::handleIprRead(), LSQ< Impl >::SplitDataRequest::handleIprRead(), TimingSimpleCPU::handleReadPacket(), LSQ< Impl >::LSQRequest::isSplit(), AtomicSimpleCPU::readMem(), Minor::LSQ::tryToSend(), LSQ< Impl >::SingleDataRequest::~SingleDataRequest(), and LSQ< Impl >::SplitDataRequest::~SplitDataRequest().

handleIprWrite()

Cycles AlphaISA::handleIprWrite ( ThreadContext *  , Packet *    )

inline

Definition at line 49 of file mmapped_ipr.hh.

Referenced by BaseKvmCPU::doMMIOAccess(), LSQ< Impl >::SingleDataRequest::handleIprWrite(), LSQ< Impl >::SplitDataRequest::handleIprWrite(), TimingSimpleCPU::handleWritePacket(), LSQ< Impl >::LSQRequest::isSplit(), Minor::LSQ::tryToSend(), AtomicSimpleCPU::writeMem(), LSQ< Impl >::SingleDataRequest::~SingleDataRequest(), and LSQ< Impl >::SplitDataRequest::~SplitDataRequest().

handleLockedRead()

template<class XC >

void AlphaISA::handleLockedRead ( XC *  xc, const RequestPtr &  req  )

inline

Definition at line 88 of file locked_mem.hh.

References MISCREG_LOCKADDR, and MISCREG_LOCKFLAG.

handleLockedSnoop()

template<class XC >

void AlphaISA::handleLockedSnoop ( XC *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

inline

Definition at line 69 of file locked_mem.hh.

References Packet::getAddr(), MISCREG_LOCKADDR, and MISCREG_LOCKFLAG.

handleLockedSnoopHit()

template<class XC >

void AlphaISA::handleLockedSnoopHit ( XC *  xc )

inline

Definition at line 96 of file locked_mem.hh.

handleLockedWrite()

template<class XC >

bool AlphaISA::handleLockedWrite ( XC *  xc, const RequestPtr &  req, Addr  cacheBlockMask  )

inline

Definition at line 102 of file locked_mem.hh.

References MISCREG_LOCKADDR, MISCREG_LOCKFLAG, and warn.

ICM_CM()

uint64_t AlphaISA::ICM_CM ( uint64_t  reg )

inline

Definition at line 97 of file ev5.hh.

Referenced by AlphaISA::TLB::translateInst().

ICSR_FPE()

bool AlphaISA::ICSR_FPE ( uint64_t  reg )

inline

Definition at line 93 of file ev5.hh.

ICSR_SDE()

bool AlphaISA::ICSR_SDE ( uint64_t  reg )

inline

Definition at line 91 of file ev5.hh.

ICSR_SPE()

int AlphaISA::ICSR_SPE ( uint64_t  reg )

inline

Definition at line 92 of file ev5.hh.

initializeIprTable()

void AlphaISA::initializeIprTable

(

)

Definition at line 129 of file ipr.cc.

References MaxInternalProcRegs, NumInternalProcRegs, and X86ISA::x.

Referenced by IprIsReadable(), and AlphaISA::ISA::ISA().

initIPRs()

void AlphaISA::initIPRs	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 69 of file ev5.cc.

References ArmISA::i, IPR_MCSR, IPR_PAL_BASE, IPR_PALtemp16, NumInternalProcRegs, PalBase, and ThreadContext::setMiscRegNoEffect().

Referenced by AlphaSystem::initState(), and RoundPage().

inUserMode()

bool AlphaISA::inUserMode ( ThreadContext *  tc )

inline

Definition at line 56 of file utility.hh.

References IPR_DTB_CM, and ThreadContext::readMiscRegNoEffect().

Referenced by BaseSimpleCPU::postExecute(), AnnotateDumpCallback::process(), and Trace::ExeTracerRecord::traceInst().

IprIsReadable()

bool AlphaISA::IprIsReadable ( int  index )

inline

Definition at line 227 of file ipr.hh.

References initializeIprTable(), IprToMiscRegIndex, MaxInternalProcRegs, MaxWriteOnlyIpr, MiscRegIndexToIpr, and NumInternalProcRegs.

IprIsWritable()

bool AlphaISA::IprIsWritable ( int  index )

inline

Definition at line 221 of file ipr.hh.

References MaxReadOnlyIpr.

IsK0Seg()

bool AlphaISA::IsK0Seg ( Addr  a )

inline

Definition at line 75 of file utility.hh.

References K0SegBase, and K0SegEnd.

Referenced by AlphaISA::RemoteGDB::acc(), and vtophys().

IsK1Seg()

bool AlphaISA::IsK1Seg ( Addr  a )

inline

Definition at line 79 of file utility.hh.

References K1SegBase, and K1SegEnd.

IsUSeg()

bool AlphaISA::IsUSeg ( Addr  a )

inline

Definition at line 72 of file utility.hh.

References USegBase, and USegEnd.

Referenced by vtophys().

ITB_ASN_ASN()

int AlphaISA::ITB_ASN_ASN ( uint64_t  reg )

inline

Definition at line 80 of file ev5.hh.

References AsnMask.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_ASMA()

bool AlphaISA::ITB_PTE_ASMA ( uint64_t  reg )

inline

Definition at line 87 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_FONR()

bool AlphaISA::ITB_PTE_FONR ( uint64_t  reg )

inline

Definition at line 84 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_FONW()

bool AlphaISA::ITB_PTE_FONW ( uint64_t  reg )

inline

Definition at line 85 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_GH()

int AlphaISA::ITB_PTE_GH ( uint64_t  reg )

inline

Definition at line 86 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_PPN()

Addr AlphaISA::ITB_PTE_PPN ( uint64_t  reg )

inline

Definition at line 81 of file ev5.hh.

References PageShift, and ULL.

Referenced by AlphaISA::ISA::setIpr().

ITB_PTE_XRE()

int AlphaISA::ITB_PTE_XRE ( uint64_t  reg )

inline

Definition at line 83 of file ev5.hh.

Referenced by AlphaISA::ISA::setIpr().

K0Seg2Phys()

Addr AlphaISA::K0Seg2Phys ( Addr  addr )

inline

Definition at line 76 of file utility.hh.

References K0SegBase.

Referenced by vtophys().

kernel_pte_lookup()

PageTableEntry AlphaISA::kernel_pte_lookup	(	PortProxy &	mem,
		Addr	ptbr,
		VAddr	vaddr
	)

Definition at line 49 of file vtophys.cc.

References DPRINTF, AlphaISA::VAddr::level1(), AlphaISA::VAddr::level2(), AlphaISA::VAddr::level3(), AlphaISA::PageTableEntry::paddr(), PortProxy::read(), and AlphaISA::PageTableEntry::valid().

Referenced by AlphaISA::RemoteGDB::acc(), and vtophys().

MCSR_SP()

uint64_t AlphaISA::MCSR_SP ( uint64_t  reg )

inline

Definition at line 89 of file ev5.hh.

Opcode()

int AlphaISA::Opcode ( MachInst  inst )

inline

Definition at line 105 of file ev5.hh.

Referenced by AlphaISA::DtbFault::invoke(), and X86ISA::opcodeTypeToStr().

PAddrIprSpace()

bool AlphaISA::PAddrIprSpace ( Addr  a )

inline

Definition at line 52 of file ev5.hh.

References ULL.

Referenced by AlphaISA::TLB::checkCacheability().

PcPAL()

bool AlphaISA::PcPAL ( Addr  addr )

inline

Definition at line 62 of file utility.hh.

Referenced by AlphaISA::RemoteGDB::acc(), AlphaISA::RemoteGDB::AlphaGdbRegCache::getRegs(), AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs(), AlphaISA::TLB::translateData(), AlphaISA::TLB::translateInst(), and vtophys().

Phys2K0Seg()

Addr AlphaISA::Phys2K0Seg ( Addr  addr )

inline

Definition at line 61 of file ev5.hh.

References K0SegBase, PAddrUncachedBit40, and PAddrUncachedMask.

Referenced by AlphaSystem::setAlphaAccess().

PteAddr()

Addr AlphaISA::PteAddr ( Addr  a )

inline

Definition at line 69 of file utility.hh.

References PteMask, and PteShift.

Referenced by AlphaISA::VAddr::level1(), AlphaISA::VAddr::level2(), and AlphaISA::VAddr::level3().

Ra()

int AlphaISA::Ra ( MachInst  inst )

inline

Definition at line 106 of file ev5.hh.

Referenced by AlphaISA::DtbFault::invoke().

RoundPage()

Addr AlphaISA::RoundPage ( Addr  addr )

inline

Definition at line 86 of file utility.hh.

References copyMiscRegs(), copyRegs(), initIPRs(), PageBytes, and skipFunction().

Referenced by AlphaISA::RemoteGDB::acc().

skipFunction()

void AlphaISA::skipFunction

(

ThreadContext *

tc

)

Definition at line 101 of file utility.cc.

References ThreadContext::pcState(), ThreadContext::readIntReg(), ReturnAddressReg, and GenericISA::SimplePCState< MachInst >::set().

Referenced by SkipFuncEvent::process(), and RoundPage().

TruncPage()

Addr AlphaISA::TruncPage ( Addr  addr )

inline

Definition at line 82 of file utility.hh.

References PageBytes.

Referenced by AlphaISA::RemoteGDB::acc().

VAddrImpl()

Addr AlphaISA::VAddrImpl ( Addr  a )

inline

Definition at line 46 of file ev5.hh.

References VAddrImplMask.

VAddrOffset()

Addr AlphaISA::VAddrOffset ( Addr  a )

inline

Definition at line 48 of file ev5.hh.

References PageOffset.

VAddrSpaceEV5()

Addr AlphaISA::VAddrSpaceEV5 ( Addr  a )

inline

Definition at line 49 of file ev5.hh.

VAddrSpaceEV6()

Addr AlphaISA::VAddrSpaceEV6 ( Addr  a )

inline

Definition at line 50 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData(), and AlphaISA::TLB::translateInst().

VAddrVPN()

Addr AlphaISA::VAddrVPN ( Addr  a )

inline

Definition at line 47 of file ev5.hh.

References PageShift.

vtophys() [1/2]

Addr AlphaISA::vtophys

(

Addr

vaddr

)

Definition at line 75 of file vtophys.cc.

References DPRINTF, IsK0Seg(), IsUSeg(), K0Seg2Phys(), and panic.

Referenced by BaseSimpleCPU::dbg_vtophys(), CheckerCPU::dbg_vtophys(), FSTranslatingPortProxy::tryMemsetBlob(), FSTranslatingPortProxy::tryReadBlob(), and FSTranslatingPortProxy::tryWriteBlob().

vtophys() [2/2]

Addr AlphaISA::vtophys	(	ThreadContext *	tc,
		Addr	addr
	)

Definition at line 91 of file vtophys.cc.

References addr, DPRINTF, ThreadContext::getPhysProxy(), IPR_PALtemp20, IsK0Seg(), K0Seg2Phys(), kernel_pte_lookup(), AlphaISA::VAddr::offset(), AlphaISA::PageTableEntry::paddr(), PalMax, PcPAL(), ThreadContext::readMiscRegNoEffect(), ULL, MipsISA::vaddr, and AlphaISA::PageTableEntry::valid().

Variable Documentation

AsnMask

const uint64_t AlphaISA::AsnMask = ULL(0xff)

Definition at line 42 of file ev5.hh.

Referenced by DTB_ASN_ASN(), and ITB_ASN_ASN().

break_ipl

int AlphaISA::break_ipl = -1

Definition at line 187 of file ev5.cc.

CurThreadInfoImplemented

const bool AlphaISA::CurThreadInfoImplemented = true

Definition at line 112 of file isa_traits.hh.

Referenced by Linux::ThreadInfo::curThreadInfo().

CurThreadInfoReg

const int AlphaISA::CurThreadInfoReg = AlphaISA::IPR_PALtemp23

Definition at line 113 of file isa_traits.hh.

Referenced by Linux::ThreadInfo::curThreadInfo().

FirstArgumentReg

const RegIndex AlphaISA::FirstArgumentReg = 16

Definition at line 85 of file registers.hh.

FramePointerReg

const RegIndex AlphaISA::FramePointerReg = 15

Definition at line 82 of file registers.hh.

Referenced by Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and Trace::TarmacTracerRecord::TraceRegEntry::updateInt().

GlobalPointerReg

const RegIndex AlphaISA::GlobalPointerReg = 29

Definition at line 78 of file registers.hh.

Referenced by AlphaProcess::initState().

GuestByteOrder

const ByteOrder AlphaISA::GuestByteOrder = LittleEndianByteOrder

Definition at line 42 of file isa_traits.hh.

Referenced by AlphaProcess::argsInit(), MipsProcess::argsInit(), RiscvProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), AbstractMemory::checkLockedAddrList(), dumpDmesgEntry(), Linux::ThreadInfo::get_data(), System::getGuestByteOrder(), AlphaISA::ProcessInfo::pid(), AlphaISA::ProcessInfo::ProcessInfo(), LinuxAlphaSystem::setDelayLoop(), and AlphaISA::ProcessInfo::task().

HasUnalignedMemAcc

const bool AlphaISA::HasUnalignedMemAcc = false

Definition at line 110 of file isa_traits.hh.

IprToMiscRegIndex

int AlphaISA::IprToMiscRegIndex

Definition at line 126 of file ipr.cc.

Referenced by IprIsReadable().

K0SegBase

const Addr AlphaISA::K0SegBase = ULL(0xfffffc0000000000)

Definition at line 66 of file isa_traits.hh.

Referenced by AlphaISA::RemoteGDB::acc(), IsK0Seg(), K0Seg2Phys(), and Phys2K0Seg().

K0SegEnd

const Addr AlphaISA::K0SegEnd = ULL(0xfffffdffffffffff)

Definition at line 67 of file isa_traits.hh.

Referenced by IsK0Seg().

K1SegBase

const Addr AlphaISA::K1SegBase = ULL(0xfffffe0000000000)

Definition at line 70 of file isa_traits.hh.

Referenced by IsK1Seg().

K1SegEnd

const Addr AlphaISA::K1SegEnd = ULL(0xffffffffffffffff)

Definition at line 71 of file isa_traits.hh.

Referenced by IsK1Seg().

MachineBytes

const int AlphaISA::MachineBytes = 8

Definition at line 107 of file isa_traits.hh.

Referenced by AlphaProcess::initState(), and PowerProcess::initState().

MaxMiscDestRegs

const int AlphaISA::MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1

Definition at line 47 of file registers.hh.

Referenced by BaseO3DynInst< Impl >::setMiscReg().

MiscRegIndexToIpr

md_ipr_names AlphaISA::MiscRegIndexToIpr

Definition at line 38 of file ipr.cc.

Referenced by IprIsReadable().

MM_STAT_ACV_MASK

const uint64_t AlphaISA::MM_STAT_ACV_MASK = ULL(0x0002)

Definition at line 103 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

MM_STAT_BAD_VA_MASK

const uint64_t AlphaISA::MM_STAT_BAD_VA_MASK = ULL(0x0020)

Definition at line 99 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

MM_STAT_DTB_MISS_MASK

const uint64_t AlphaISA::MM_STAT_DTB_MISS_MASK = ULL(0x0010)

Definition at line 100 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

MM_STAT_FONR_MASK

const uint64_t AlphaISA::MM_STAT_FONR_MASK = ULL(0x0004)

Definition at line 102 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

MM_STAT_FONW_MASK

const uint64_t AlphaISA::MM_STAT_FONW_MASK = ULL(0x0008)

Definition at line 101 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

MM_STAT_WR_MASK

const uint64_t AlphaISA::MM_STAT_WR_MASK = ULL(0x0001)

Definition at line 104 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData().

NPtePage

const Addr AlphaISA::NPtePage = ULL(1) << NPtePageShift

Definition at line 58 of file isa_traits.hh.

NPtePageShift

const Addr AlphaISA::NPtePageShift = PageShift - PteShift

Definition at line 57 of file isa_traits.hh.

Referenced by AlphaISA::VAddr::level1(), and AlphaISA::VAddr::level2().

NumCCRegs

const int AlphaISA::NumCCRegs = 0

Definition at line 99 of file registers.hh.

Referenced by ThreadContext::compare(), copyRegs(), Minor::Scoreboard::findIndex(), FullO3CPU< O3CPUImpl >::FullO3CPU(), UnifiedRenameMap::init(), FullO3CPU< O3CPUImpl >::insertThread(), PhysRegFile::PhysRegFile(), SimpleThread::readCCReg(), serialize(), SimpleThread::setCCReg(), and unserialize().

NumFloatArchRegs

const int AlphaISA::NumFloatArchRegs = 32

Definition at line 91 of file registers.hh.

Referenced by AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs().

NumFloatRegs

const int AlphaISA::NumFloatRegs = NumFloatArchRegs

Definition at line 94 of file registers.hh.

Referenced by ThreadContext::compare(), copyRegs(), Minor::Scoreboard::findIndex(), FullO3CPU< O3CPUImpl >::FullO3CPU(), UnifiedRenameMap::init(), FullO3CPU< O3CPUImpl >::insertThread(), SimpleThread::readFloatReg(), serialize(), SimpleThread::setFloatReg(), and unserialize().

NumIntArchRegs

const int AlphaISA::NumIntArchRegs = 32

Definition at line 89 of file registers.hh.

Referenced by SparcISA::doNormalFault(), SparcISA::doREDFault(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), SparcProcess::initState(), and SparcProcess::setSyscallReturn().

NumIntRegs

const int AlphaISA::NumIntRegs = NumIntArchRegs + NumPALShadowRegs

Definition at line 93 of file registers.hh.

Referenced by ThreadContext::compare(), copyRegs(), Minor::Scoreboard::findIndex(), FullO3CPU< O3CPUImpl >::FullO3CPU(), UnifiedRenameMap::init(), FullO3CPU< O3CPUImpl >::insertThread(), SimpleThread::readIntReg(), serialize(), SimpleThread::setIntReg(), and unserialize().

NumMiscRegs

const int AlphaISA::NumMiscRegs = NUM_MISCREGS

Definition at line 100 of file registers.hh.

Referenced by ThreadContext::compare(), and PhysRegFile::PhysRegFile().

NumPALShadowRegs

const int AlphaISA::NumPALShadowRegs = 8

Definition at line 90 of file registers.hh.

NumVecElemPerVecReg

constexpr unsigned AlphaISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

Definition at line 54 of file registers.hh.

Referenced by FullO3CPU< O3CPUImpl >::FullO3CPU(), InstructionQueue< Impl >::InstructionQueue(), and UnifiedRenameMap::switchFreeList().

NumVecPredRegs

const int AlphaISA::NumVecPredRegs = 1

Definition at line 97 of file registers.hh.

Referenced by ThreadContext::compare(), FullO3CPU< O3CPUImpl >::FullO3CPU(), SimpleThread::getWritableVecPredReg(), UnifiedRenameMap::init(), SimpleThread::readVecPredReg(), serialize(), SimpleThread::setVecPredReg(), and unserialize().

NumVecRegs

const int AlphaISA::NumVecRegs = 1

Definition at line 95 of file registers.hh.

Referenced by ThreadContext::compare(), Minor::Scoreboard::findIndex(), FullO3CPU< O3CPUImpl >::FullO3CPU(), SimpleThread::getWritableVecReg(), UnifiedRenameMap::init(), SimpleThread::readVecElem(), SimpleThread::readVecLane(), SimpleThread::readVecReg(), serialize(), SimpleThread::setVecElem(), SimpleThread::setVecLaneT(), SimpleThread::setVecReg(), UnifiedRenameMap::switchFreeList(), UnifiedRenameMap::switchMode(), and unserialize().

PAddrImplBits

const int AlphaISA::PAddrImplBits = 44

Definition at line 53 of file ev5.hh.

PAddrImplMask

const Addr AlphaISA::PAddrImplMask = (ULL(1) << PAddrImplBits) - 1

Definition at line 54 of file ev5.hh.

Referenced by AlphaISA::TLB::translateData(), and AlphaISA::TLB::translateInst().

PAddrUncachedBit39

const Addr AlphaISA::PAddrUncachedBit39 = ULL(0x8000000000)

Definition at line 55 of file ev5.hh.

PAddrUncachedBit40

const Addr AlphaISA::PAddrUncachedBit40 = ULL(0x10000000000)

Definition at line 56 of file ev5.hh.

Referenced by Phys2K0Seg(), AlphaISA::TLB::translateData(), and AlphaISA::TLB::translateInst().

PAddrUncachedBit43

const Addr AlphaISA::PAddrUncachedBit43 = ULL(0x80000000000)

Definition at line 57 of file ev5.hh.

Referenced by AlphaISA::TLB::checkCacheability().

PAddrUncachedMask

const Addr AlphaISA::PAddrUncachedMask = ULL(0x807ffffffff)

Definition at line 58 of file ev5.hh.

Referenced by AlphaISA::TLB::checkCacheability(), and Phys2K0Seg().

PageBytes

const Addr AlphaISA::PageBytes = ULL(1) << PageShift

Definition at line 47 of file isa_traits.hh.

Referenced by AlphaISA::RemoteGDB::acc(), Process::allocateMem(), AlphaProcess::AlphaProcess(), AlphaProcess::argsInit(), RiscvProcess::argsInit(), ArmProcess32::ArmProcess32(), ArmProcess64::ArmProcess64(), brkFunc(), TLBCoalescer::canCoalesce(), Process::fixupStackFault(), DecodeCache::AddrMap< RefCountingPtr >::getPage(), System::getPageBytes(), getpagesizeFunc(), X86ISA::GpuTLB::handleFuncTranslationReturn(), AlphaProcess::initState(), MipsProcess::initState(), PowerProcess::initState(), RiscvProcess64::initState(), RiscvProcess32::initState(), ArmLinuxProcess32::initState(), ArmProcess32::initState(), ArmProcess64::initState(), Sparc32Process::initState(), Sparc64Process::initState(), X86ISA::GpuTLB::issueTLBLookup(), DecodeCache::AddrMap< RefCountingPtr >::lookup(), MipsProcess::MipsProcess(), Shader::mmap(), mmapFunc(), mremapFunc(), PowerProcess::PowerProcess(), TLBCoalescer::processProbeTLBEvent(), TLBCoalescer::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), Process::replicatePage(), RiscvProcess32::RiscvProcess32(), RiscvProcess64::RiscvProcess64(), RoundPage(), TruncPage(), SETranslatingPortProxy::tryMemsetBlob(), FSTranslatingPortProxy::tryMemsetBlob(), SETranslatingPortProxy::tryReadBlob(), FSTranslatingPortProxy::tryReadBlob(), SETranslatingPortProxy::tryWriteBlob(), FSTranslatingPortProxy::tryWriteBlob(), Process::updateBias(), ComputeUnit::updatePageDivergenceDist(), and TLBCoalescer::updatePhysAddresses().

PageMask

const Addr AlphaISA::PageMask = ~(PageBytes - 1)

Definition at line 48 of file isa_traits.hh.

Referenced by AlphaISA::VAddr::page().

PageOffset

const Addr AlphaISA::PageOffset = PageBytes - 1

Definition at line 49 of file isa_traits.hh.

Referenced by AlphaISA::VAddr::offset(), and VAddrOffset().

PageShift

const Addr AlphaISA::PageShift = 13

Definition at line 46 of file isa_traits.hh.

Referenced by System::allocPhysPages(), X86ISA::GpuTLB::demapPage(), DTB_PTE_PPN(), System::freeMemSize(), System::getPageShift(), X86ISA::GpuTLB::insert(), ITB_PTE_PPN(), AlphaISA::VAddr::level1(), AlphaISA::VAddr::level2(), AlphaISA::VAddr::level3(), X86ISA::GpuTLB::lookup(), X86ISA::GpuTLB::lookupIt(), AlphaISA::PageTableEntry::paddr(), AlphaISA::TlbEntry::pageStart(), ComputeUnit::DTLBPort::recvTimingResp(), AlphaISA::TLB::translateData(), AlphaISA::TLB::translateInst(), VAddrVPN(), and AlphaISA::VAddr::vpn().

PalBase

const Addr AlphaISA::PalBase = 0x4000

Definition at line 108 of file ev5.hh.

Referenced by initIPRs().

PalMax

const Addr AlphaISA::PalMax = 0x10000

Definition at line 109 of file ev5.hh.

Referenced by vtophys().

ProcedureValueReg

const RegIndex AlphaISA::ProcedureValueReg = 27

Definition at line 79 of file registers.hh.

PteMask

const Addr AlphaISA::PteMask = NPtePage - 1

Definition at line 59 of file isa_traits.hh.

Referenced by PteAddr().

PteShift

const Addr AlphaISA::PteShift = 3

Definition at line 56 of file isa_traits.hh.

Referenced by PteAddr().

reg_redir

const int AlphaISA::reg_redir

Initial value:

= {
     0, 1, 2, 3, 4, 5, 6, 7,
     32, 33, 34, 35, 36, 37, 38, 15,
     16, 17, 18, 19, 20, 21, 22, 23,
     24, 39, 26, 27, 28, 29, 30, 31 }

Definition at line 37 of file regredir.cc.

Referenced by AlphaISA::RemoteGDB::AlphaGdbRegCache::getRegs(), and AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs().

ReturnAddressReg

const RegIndex AlphaISA::ReturnAddressReg = 26

Definition at line 80 of file registers.hh.

Referenced by AlphaISA::StackTrace::decodePrologue(), AnnotateDumpCallback::process(), skipFunction(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and Trace::TarmacTracerRecord::TraceRegEntry::updateInt().

ReturnValueReg

const RegIndex AlphaISA::ReturnValueReg = 0

Definition at line 81 of file registers.hh.

Referenced by AlphaProcess::setSyscallReturn(), PowerProcess::setSyscallReturn(), MipsProcess::setSyscallReturn(), SparcProcess::setSyscallReturn(), ArmProcess32::setSyscallReturn(), and ArmProcess64::setSyscallReturn().

StackPointerReg

const RegIndex AlphaISA::StackPointerReg = 30

Definition at line 77 of file registers.hh.

Referenced by AlphaLinux::archClone(), AlphaProcess::argsInit(), RiscvProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), getArgument(), AlphaISA::StackTrace::trace(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt(), and Trace::TarmacTracerRecord::TraceRegEntry::updateInt().

SyscallNumReg

const RegIndex AlphaISA::SyscallNumReg = 0

Definition at line 84 of file registers.hh.

Referenced by RiscvLinuxProcess64::syscall(), and RiscvLinuxProcess32::syscall().

SyscallPseudoReturnReg

const RegIndex AlphaISA::SyscallPseudoReturnReg = 20

Definition at line 86 of file registers.hh.

Referenced by cloneFunc(), getgidPseudoFunc(), getpidPseudoFunc(), getuidPseudoFunc(), pipeImpl(), and RiscvProcess::setSyscallReturn().

SyscallSuccessReg

const RegIndex AlphaISA::SyscallSuccessReg = 19

Definition at line 87 of file registers.hh.

Referenced by cloneFunc(), AlphaProcess::setSyscallReturn(), and MipsProcess::setSyscallReturn().

TotalNumRegs

const int AlphaISA::TotalNumRegs

Initial value:

=
    NumIntRegs + NumFloatRegs + NumMiscRegs

Definition at line 102 of file registers.hh.

USegBase

const Addr AlphaISA::USegBase = ULL(0x0)

Definition at line 62 of file isa_traits.hh.

Referenced by IsUSeg().

USegEnd

const Addr AlphaISA::USegEnd = ULL(0x000003ffffffffff)

Definition at line 63 of file isa_traits.hh.

Referenced by IsUSeg().

VAddrImplBits

const int AlphaISA::VAddrImplBits = 43

Definition at line 43 of file ev5.hh.

VAddrImplMask

const Addr AlphaISA::VAddrImplMask = (ULL(1) << VAddrImplBits) - 1

Definition at line 44 of file ev5.hh.

Referenced by VAddrImpl().

VAddrUnImplMask

const Addr AlphaISA::VAddrUnImplMask = ~VAddrImplMask

Definition at line 45 of file ev5.hh.

Referenced by AlphaISA::TLB::validVirtualAddress().

VecPredRegHasPackedRepr

constexpr bool AlphaISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

Definition at line 62 of file registers.hh.

Referenced by Trace::InstRecord::setData().

VecPredRegSizeBits

constexpr size_t AlphaISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

Definition at line 61 of file registers.hh.

Referenced by Trace::InstRecord::setData(), and Trace::ExeTracerRecord::traceInst().

VecRegSizeBytes

constexpr size_t AlphaISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

Definition at line 55 of file registers.hh.

Referenced by Trace::ExeTracerRecord::traceInst().

ZeroReg

const RegIndex AlphaISA::ZeroReg = 31

Definition at line 75 of file registers.hh.

Referenced by Minor::ExecContext::ExecContext(), FullO3CPU< O3CPUImpl >::FullO3CPU(), RegId::isZeroReg(), Minor::Scoreboard::markupInstDests(), BaseSimpleCPU::preExecute(), and Checker< O3CPUImpl >::verify().