gem5  v19.0.0.0
static_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2006-2007 The Regents of The University of Michigan
3  * All rights reserved.
4  * Copyright 2017 Google Inc.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * Authors: Gabe Black
30  */
31 #ifndef __ARCH_SPARC_INSTS_STATIC_INST_HH__
32 #define __ARCH_SPARC_INSTS_STATIC_INST_HH__
33 
34 #include <cstdint>
35 
36 #include "base/trace.hh"
37 #include "cpu/exec_context.hh"
38 #include "cpu/static_inst.hh"
39 
40 namespace SparcISA
41 {
42 
44 {
45  Always=0x8,
46  Never=0x0,
47  NotEqual=0x9,
48  Equal=0x1,
49  Greater=0xA,
52  Less=0x3,
56  CarrySet=0x5,
57  Positive=0xE,
58  Negative=0x6,
61 };
62 
63 extern const char *CondTestAbbrev[];
64 
66 {
67  FAlways=0x8,
68  FNever=0x0,
70  FGreater=0x6,
72  FLess=0x4,
75  FNotEqual=0x1,
76  FEqual=0x9,
83 };
84 
89 {
90  protected:
92 
93  std::string generateDisassembly(
94  Addr pc, const SymbolTable *symtab) const override;
95 
96  static void printMnemonic(std::ostream &os, const char *mnemonic);
97  static void printReg(std::ostream &os, RegId reg);
98 
99  void printSrcReg(std::ostream &os, int reg) const;
100  void printDestReg(std::ostream &os, int reg) const;
101 
102  void printRegArray(std::ostream &os,
103  const RegId indexArray[], int num) const;
104 
105  void advancePC(PCState &pcState) const override;
106 
107  static bool passesFpCondition(uint32_t fcc, uint32_t condition);
108  static bool passesCondition(uint32_t codes, uint32_t condition);
109 
110  size_t
111  asBytes(void *buf, size_t size) override
112  {
113  return simpleAsBytes(buf, size, machInst);
114  }
115 };
116 
117 }
118 
119 #endif //__ARCH_SPARC_INSTS_STATIC_INST_HH__
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:97
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:58
Bitfield< 5, 3 > reg
Definition: types.hh:89
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:251
void advancePC(PCState &pcState) const override
Definition: static_inst.cc:77
size_t asBytes(void *buf, size_t size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:111
static bool passesFpCondition(uint32_t fcc, uint32_t condition)
Definition: static_inst.cc:279
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:244
const char * CondTestAbbrev[]
Definition: static_inst.cc:37
Bitfield< 17 > os
Definition: misc.hh:805
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:229
Bitfield< 4 > pc
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:83
Base class for all SPARC static instructions.
Definition: static_inst.hh:88
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
void printDestReg(std::ostream &os, int reg) const
Definition: static_inst.cc:90
Definition: asi.cc:34
void printRegArray(std::ostream &os, const RegId indexArray[], int num) const
Definition: static_inst.cc:64
Base, ISA-independent static instruction class.
Definition: static_inst.hh:83
static bool passesCondition(uint32_t codes, uint32_t condition)
Definition: static_inst.cc:324
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: static_inst.hh:263
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:79
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:341

Generated on Fri Feb 28 2020 16:26:57 for gem5 by doxygen 1.8.13