gem5  v19.0.0.0
tlb.hh
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29 
30 #ifndef __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
31 #define __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
32 
33 #include "arch/generic/tlb.hh"
34 
35 namespace Iris
36 {
37 
38 class TLB : public BaseTLB
39 {
40  public:
41  TLB(const Params *p) : BaseTLB(p) {}
42 
43  void demapPage(Addr vaddr, uint64_t asn) override {}
44  void flushAll() override {}
45  void takeOverFrom(BaseTLB *otlb) override {}
46 
48  const RequestPtr &req, ::ThreadContext *tc, Mode mode) override;
50  const RequestPtr &req, ::ThreadContext *tc, Mode mode) override;
51  void translateTiming(
52  const RequestPtr &req, ::ThreadContext *tc,
53  Translation *translation, Mode mode) override;
54 
55  Fault
57  const RequestPtr &req, ::ThreadContext *tc, Mode mode) const override
58  {
59  return NoFault;
60  }
61 };
62 
63 } // namespace Iris
64 
65 #endif // __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
decltype(nullptr) constexpr NoFault
Definition: types.hh:245
SimObjectParams Params
Definition: sim_object.hh:113
std::shared_ptr< Request > RequestPtr
Definition: request.hh:83
Fault finalizePhysical(const RequestPtr &req, ::ThreadContext *tc, Mode mode) const override
Definition: tlb.hh:56
Bitfield< 4, 0 > mode
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:43
Definition: tlb.hh:52
TLB(const Params *p)
Definition: tlb.hh:41
void translateTiming(const RequestPtr &req, ::ThreadContext *tc, Translation *translation, Mode mode) override
Definition: tlb.cc:64
Definition: tlb.hh:38
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Fault translateFunctional(const RequestPtr &req, ::ThreadContext *tc, Mode mode) override
Definition: tlb.cc:38
Mode
Definition: tlb.hh:59
Fault translateAtomic(const RequestPtr &req, ::ThreadContext *tc, Mode mode) override
Definition: tlb.cc:57
void flushAll() override
Remove all entries from the TLB.
Definition: tlb.hh:44
Bitfield< 0 > p
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.hh:45
Definition: cpu.cc:36

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