#include <static_inst.hh>

Inheritance diagram for ArmISA::ArmStaticInst:

Public Member Functions
virtual void	annotateFault (ArmFault *fault)

uint8_t	getIntWidth () const

ssize_t	instSize () const
	Returns the byte size of current instruction. More...

MachInst	encoding () const
	Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode. More...

size_t	asBytes (void *buf, size_t max_size) override
	Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...

Public Member Functions inherited from StaticInst
void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue. More...

const RegId &	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg. More...

const RegId &	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg. More...

virtual	~StaticInst ()

virtual Fault	execute (ExecContext xc, Trace::InstRecord traceData) const =0

virtual Fault	initiateAcc (ExecContext xc, Trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, Trace::InstRecord *traceData) const

virtual void	advancePC (TheISA::PCState &pcState) const =0

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc. More...

virtual TheISA::PCState	branchTarget (const TheISA::PCState &pc) const
	Return the target address for a PC-relative branch. More...

virtual TheISA::PCState	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump). More...

bool	hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
	Return true if the instruction is a control transfer, and if so, return the target address as well. More...

virtual const std::string &	disassemble (Addr pc, const SymbolTable *symtab=0) const
	Return string representation of disassembled instruction. More...

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream. More...

std::string	getName ()
	Return name of machine instruction. More...

int8_t	numSrcRegs () const
	Number of source registers. More...

int8_t	numDestRegs () const
	Number of destination registers. More...

int8_t	numFPDestRegs () const
	Number of floating-point destination regs. More...

int8_t	numIntDestRegs () const
	Number of integer destination regs. More...

int8_t	numVecDestRegs () const
	Number of vector destination regs. More...

int8_t	numVecElemDestRegs () const
	Number of vector element destination regs. More...

int8_t	numVecPredDestRegs () const
	Number of predicate destination regs. More...

int8_t	numCCDestRegs () const
	Number of coprocesor destination regs. More...

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isCC () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isCondDelaySlot () const

bool	isThreadSync () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isMemBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isIprAccess () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isMicroBranch () const

Public Member Functions inherited from RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref () const
	Increment the reference count. More...

void	decref () const
	Decrement the reference count and destroy the object if all references are gone. More...

Static Public Member Functions
static unsigned	getCurSveVecLenInBits (ThreadContext *tc)

static unsigned	getCurSveVecLenInQWords (ThreadContext *tc)

template<typename T >
static unsigned	getCurSveVecLen (ThreadContext *tc)

Protected Member Functions
int32_t	shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int32_t	shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int64_t	shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const

int64_t	extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const

	ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)

void	printIntReg (std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
	Print a register name for disassembly given the unique dependence tag number (FP or int). More...

void	printFloatReg (std::ostream &os, RegIndex reg_idx) const

void	printVecReg (std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const

void	printVecPredReg (std::ostream &os, RegIndex reg_idx) const

void	printCCReg (std::ostream &os, RegIndex reg_idx) const

void	printMiscReg (std::ostream &os, RegIndex reg_idx) const

void	printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const

void	printTarget (std::ostream &os, Addr target, const SymbolTable *symtab) const

void	printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const

void	printMemSymbol (std::ostream &os, const SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const

void	printShiftOperand (std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const

void	printExtendOperand (bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const

void	printPFflags (std::ostream &os, int flag) const

void	printDataInst (std::ostream &os, bool withImm) const

void	printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const

void	advancePC (PCState &pcState) const override

std::string	generateDisassembly (Addr pc, const SymbolTable *symtab) const override
	Internal function to generate disassembly string. More...

Fault	disabledFault () const

bool	isWFxTrapping (ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const

Fault	softwareBreakpoint32 (ExecContext *xc, uint16_t imm) const
	Trigger a Software Breakpoint. More...

Fault	advSIMDFPAccessTrap64 (ExceptionLevel el) const
	Trap an access to Advanced SIMD or FP registers due to access control bits. More...

Fault	checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const
	Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. More...

Fault	checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...

Fault	checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
	Check if a VFP/SIMD access from aarch32 should be allowed. More...

Fault	checkForWFxTrap32 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch32 should be trapped. More...

Fault	checkForWFxTrap64 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch64 should be trapped. More...

Fault	trapWFx (ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
	WFE/WFI trapping helper function. More...

Fault	checkSETENDEnabled (ThreadContext *tc, CPSR cpsr) const
	Check if SETEND instruction execution in aarch32 should be trapped. More...

Fault	undefinedFault32 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch32. More...

Fault	undefinedFault64 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch64. More...

Fault	sveAccessTrap (ExceptionLevel el) const
	Trap an access to SVE registers due to access control bits. More...

Fault	checkSveTrap (ThreadContext *tc, CPSR cpsr) const
	Check an SVE access against CPTR_EL2 and CPTR_EL3. More...

Fault	checkSveEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...

CPSR	getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const
	Get the new PSTATE from a SPSR register in preparation for an exception return. More...

bool	generalExceptionsToAArch64 (ThreadContext *tc, ExceptionLevel pstateEL) const
	Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64. More...

Protected Member Functions inherited from StaticInst
	StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
	Constructor. More...

template<typename T >
size_t	simpleAsBytes (void *buf, size_t max_size, const T &t)

Static Protected Member Functions
template<int width>
static bool	saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	satInt (int32_t &res, int64_t op, int width)

template<int width>
static bool	uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	uSatInt (int32_t &res, int64_t op, int width)

static uint32_t	cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)

static uint32_t	spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)

static Addr	readPC (ExecContext *xc)

static void	setNextPC (ExecContext *xc, Addr val)

template<class T >
static T	cSwap (T val, bool big)

template<class T , class E >
static T	cSwap (T val, bool big)

static void	setIWNextPC (ExecContext *xc, Addr val)

static void	setAIWNextPC (ExecContext *xc, Addr val)

Protected Attributes
bool	aarch64

uint8_t	intWidth

Protected Attributes inherited from StaticInst
std::bitset< Num_Flags >	flags
	Flag values for this instruction. More...

OpClass	_opClass
	See opClass(). More...

int8_t	_numSrcRegs
	See numSrcRegs(). More...

int8_t	_numDestRegs
	See numDestRegs(). More...

RegId	_destRegIdx [MaxInstDestRegs]
	See destRegIdx(). More...

RegId	_srcRegIdx [MaxInstSrcRegs]
	See srcRegIdx(). More...

const char *	mnemonic
	Base mnemonic (e.g., "add"). More...

std::string *	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()). More...

int8_t	_numFPDestRegs
	The following are used to track physical register usage for machines with separate int & FP reg files. More...

int8_t	_numIntDestRegs

int8_t	_numCCDestRegs

int8_t	_numVecDestRegs
	To use in architectures with vector register file. More...

int8_t	_numVecElemDestRegs

int8_t	_numVecPredDestRegs

Additional Inherited Members
Public Types inherited from StaticInst
enum	{ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }

typedef TheISA::ExtMachInst	ExtMachInst
	Binary extended machine instruction type. More...

Public Attributes inherited from StaticInst
const ExtMachInst	machInst
	The binary machine instruction. More...

Static Public Attributes inherited from StaticInst
static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object. More...

static StaticInstPtr	nopStaticInstPtr = new NopStaticInst
	Pointer to a statically allocated generic "nop" instruction object. More...

Detailed Description

Definition at line 59 of file static_inst.hh.

Constructor & Destructor Documentation

◆ ArmStaticInst()

ArmISA::ArmStaticInst::ArmStaticInst	(	const char *	mnem,
		ExtMachInst	_machInst,
		OpClass	__opClass
	)

inlineprotected

Definition at line 146 of file static_inst.hh.

References addr, bits(), ArmISA::COND_UC, ArmISA::imm, StaticInst::machInst, X86ISA::os, printCCReg(), printCondition(), printDataInst(), printExtendOperand(), printFloatReg(), printIntReg(), printMemSymbol(), printMiscReg(), printMnemonic(), printPFflags(), printShiftOperand(), printTarget(), printVecPredReg(), printVecReg(), ArmISA::rd, ArmISA::rm, ArmISA::rn, ArmISA::rs, ArmISA::s, and type.

Member Function Documentation

◆ advancePC()

void ArmISA::ArmStaticInst::advancePC ( PCState & pcState ) const

inlineoverrideprotected

Definition at line 194 of file static_inst.hh.

References generateDisassembly(), and MipsISA::pc.

◆ advSIMDFPAccessTrap64()

Fault ArmISA::ArmStaticInst::advSIMDFPAccessTrap64 ( ExceptionLevel el ) const

protected

Trap an access to Advanced SIMD or FP registers due to access control bits.

See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the ARM ARM psueodcode library.

Parameters

el	Target EL for the trap

Definition at line 648 of file static_inst.cc.

References ArmISA::EC_TRAPPED_SIMD_FP, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, and panic.

Referenced by checkAdvSIMDOrFPEnabled32(), checkFPAdvSIMDEnabled64(), checkFPAdvSIMDTrap64(), and disabledFault().

◆ annotateFault()

virtual void ArmISA::ArmStaticInst::annotateFault ( ArmFault * fault )

inlinevirtual

Definition at line 511 of file static_inst.hh.

Referenced by ArmISA::ArmFault::instrAnnotate().

◆ asBytes()

size_t ArmISA::ArmStaticInst::asBytes	(	void *	buf,
		size_t	max_size
	)

inlineoverridevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented from StaticInst.

Definition at line 539 of file static_inst.hh.

References getCurSveVecLenInBits(), StaticInst::machInst, and StaticInst::simpleAsBytes().

◆ checkAdvSIMDOrFPEnabled32()

Fault ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr,
		NSACR	nsacr,
		FPEXC	fpexc,
		bool	fpexc_check,
		bool	advsimd
	)		const

protected

Check if a VFP/SIMD access from aarch32 should be allowed.

See aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled in the ARM ARM psueodcode library.

Definition at line 698 of file static_inst.cc.

References advSIMDFPAccessTrap64(), checkFPAdvSIMDEnabled64(), checkFPAdvSIMDTrap64(), ArmISA::currEL(), disabledFault(), ArmISA::EC_TRAPPED_HCPTR, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs64(), ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmISA::inSecureState(), StaticInst::machInst, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_HCPTR, StaticInst::mnemonic, NoFault, and ThreadContext::readMiscReg().

Referenced by disabledFault().

◆ checkForWFxTrap32()

Fault ArmISA::ArmStaticInst::checkForWFxTrap32	(	ThreadContext *	tc,
		ExceptionLevel	tgtEl,
		bool	isWfe
	)		const

protected

Check if WFE/WFI instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 802 of file static_inst.cc.

References checkForWFxTrap64(), ArmISA::EC_TRAPPED_WFI_WFE, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs64(), ArmSystem::haveEL(), isWFxTrapping(), StaticInst::machInst, StaticInst::mnemonic, NoFault, and panic.

Referenced by disabledFault(), and trapWFx().

◆ checkForWFxTrap64()

Fault ArmISA::ArmStaticInst::checkForWFxTrap64	(	ThreadContext *	tc,
		ExceptionLevel	tgtEl,
		bool	isWfe
	)		const

protected

Check if WFE/WFI instruction execution in aarch64 should be trapped.

See aarch64/exceptions/traps/AArch64.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 842 of file static_inst.cc.

References ArmISA::EC_TRAPPED_WFI_WFE, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmSystem::haveEL(), isWFxTrapping(), StaticInst::machInst, NoFault, and panic.

Referenced by checkForWFxTrap32(), and disabledFault().

◆ checkFPAdvSIMDEnabled64()

Fault ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr
	)		const

protected

Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the ARM ARM psueodcode library.

Definition at line 686 of file static_inst.cc.

References advSIMDFPAccessTrap64(), checkFPAdvSIMDTrap64(), ArmISA::currEL(), ArmISA::el, ArmISA::EL0, and ArmISA::EL1.

Referenced by checkAdvSIMDOrFPEnabled32(), and disabledFault().

◆ checkFPAdvSIMDTrap64()

Fault ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64	(	ThreadContext *	tc,
		CPSR	cpsr
	)		const

protected

Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the ARM ARM psueodcode library.

Definition at line 668 of file static_inst.cc.

References advSIMDFPAccessTrap64(), ArmISA::EL2, ArmISA::EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmISA::inSecureState(), ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, NoFault, and ThreadContext::readMiscReg().

Referenced by checkAdvSIMDOrFPEnabled32(), checkFPAdvSIMDEnabled64(), and disabledFault().

◆ checkSETENDEnabled()

Fault ArmISA::ArmStaticInst::checkSETENDEnabled	(	ThreadContext *	tc,
		CPSR	cpsr
	)		const

protected

Check if SETEND instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.CheckSETENDEnabled in the ARM ARM pseudocode library.

Definition at line 901 of file static_inst.cc.

References ArmISA::currEL(), ArmISA::EL2, ArmISA::inSecureState(), ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_SCTLR, NoFault, ThreadContext::readMiscRegNoEffect(), ArmISA::sed, ArmISA::snsBankedIndex(), and undefinedFault32().

Referenced by disabledFault().

◆ checkSveEnabled()

Fault ArmISA::ArmStaticInst::checkSveEnabled	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr
	)		const

protected

Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Definition at line 1009 of file static_inst.cc.

References checkSveTrap(), ArmISA::el, ArmISA::EL0, ArmISA::EL1, and sveAccessTrap().

Referenced by disabledFault().

◆ checkSveTrap()

Fault ArmISA::ArmStaticInst::checkSveTrap	(	ThreadContext *	tc,
		CPSR	cpsr
	)		const

protected

Check an SVE access against CPTR_EL2 and CPTR_EL3.

Definition at line 989 of file static_inst.cc.

References ArmISA::el, ArmISA::EL2, ArmISA::EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, NoFault, ThreadContext::readMiscReg(), and sveAccessTrap().

Referenced by checkSveEnabled(), and disabledFault().

◆ cpsrWriteByInstr()

static uint32_t ArmISA::ArmStaticInst::cpsrWriteByInstr	(	CPSR	cpsr,
		uint32_t	val,
		SCR	scr,
		NSACR	nsacr,
		uint8_t	byteMask,
		bool	affectState,
		bool	nmfi,
		ThreadContext *	tc
	)

inlinestaticprotected

Definition at line 203 of file static_inst.hh.

References ArmISA::badMode(), bits(), ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmISA::inSecureState(), ArmISA::mask, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_MON, ArmISA::MODE_USER, and warn_once.

◆ cSwap() [1/2]

template<class T >

static T ArmISA::ArmStaticInst::cSwap	(	T	val,
		bool	big
	)

inlinestaticprotected

Definition at line 314 of file static_inst.hh.

References letobe(), and X86ISA::val.

◆ cSwap() [2/2]

template<class T , class E >

static T ArmISA::ArmStaticInst::cSwap	(	T	val,
		bool	big
	)

inlinestaticprotected

Definition at line 325 of file static_inst.hh.

References RefCounted::count, X86ISA::E, htole(), ArmISA::i, letobe(), and letoh().

◆ disabledFault()

Fault ArmISA::ArmStaticInst::disabledFault ( ) const

inlineprotected

◆ encoding()

MachInst ArmISA::ArmStaticInst::encoding ( ) const

inline

Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode.

Definition at line 533 of file static_inst.hh.

References instSize(), StaticInst::machInst, and ArmISA::mask.

Referenced by UnknownOp64::generateDisassembly(), and UnknownOp::generateDisassembly().

◆ extendReg64()

int64_t ArmISA::ArmStaticInst::extendReg64	(	uint64_t	base,
		ArmExtendType	type,
		uint64_t	shiftAmt,
		uint8_t	width
	)		const

protected

Definition at line 131 of file static_inst.cc.

References bits(), ArmISA::len, ArmISA::mask, ArmISA::SXTB, ArmISA::SXTH, ArmISA::SXTW, ArmISA::SXTX, ArmISA::UXTB, ArmISA::UXTH, ArmISA::UXTW, and ArmISA::UXTX.

◆ generalExceptionsToAArch64()

bool ArmISA::ArmStaticInst::generalExceptionsToAArch64	(	ThreadContext *	tc,
		ExceptionLevel	pstateEL
	)		const

protected

Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64.

See aarch32/exceptions/exceptions/AArch32.GeneralExceptionsToAArch64 in the ARM ARM pseudocode library.

Definition at line 1154 of file static_inst.cc.

References ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::ELIs32(), ArmSystem::haveEL(), ArmISA::inSecureState(), ArmISA::MISCREG_HCR_EL2, and ThreadContext::readMiscReg().

Referenced by disabledFault(), and undefinedFault32().

◆ generateDisassembly()

std::string ArmISA::ArmStaticInst::generateDisassembly	(	Addr	pc,
		const SymbolTable *	symtab
	)		const

overrideprotectedvirtual

Internal function to generate disassembly string.

Implements StaticInst.

Definition at line 621 of file static_inst.cc.

References printMnemonic(), and ArmISA::ss.

Referenced by advancePC(), ArmISA::RfeOp::fetchMicroop(), ArmISA::SrsOp::fetchMicroop(), ArmISA::MicroIntImmOp::MicroIntImmOp(), ArmISA::MicroIntImmXOp::MicroIntImmXOp(), ArmISA::MicroIntMov::MicroIntMov(), ArmISA::MicroIntOp::MicroIntOp(), ArmISA::MicroIntRegXOp::MicroIntRegXOp(), ArmISA::MicroMemOp::MicroMemOp(), ArmISA::MicroMemPairOp::MicroMemPairOp(), and ArmISA::MicroSetPCCPSR::MicroSetPCCPSR().

◆ getCurSveVecLen()

template<typename T >

static unsigned ArmISA::ArmStaticInst::getCurSveVecLen ( ThreadContext * tc )

inlinestatic

Definition at line 554 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getCurSveVecLenInBits()

unsigned ArmISA::ArmStaticInst::getCurSveVecLenInBits ( ThreadContext * tc )

static

Definition at line 1167 of file static_inst.cc.

References ArmISA::ISA::getCurSveVecLenInBits(), and ThreadContext::getIsaPtr().

Referenced by asBytes(), getCurSveVecLen(), and getCurSveVecLenInQWords().

◆ getCurSveVecLenInQWords()

static unsigned ArmISA::ArmStaticInst::getCurSveVecLenInQWords ( ThreadContext * tc )

inlinestatic

Definition at line 547 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getIntWidth()

uint8_t ArmISA::ArmStaticInst::getIntWidth ( ) const

inline

Definition at line 514 of file static_inst.hh.

References intWidth.

◆ getPSTATEFromPSR()

CPSR ArmISA::ArmStaticInst::getPSTATEFromPSR	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPSR	spsr
	)		const

protected

Get the new PSTATE from a SPSR register in preparation for an exception return.

See shared/functions/system/SetPSTATEFromPSR in the ARM ARM pseudocode library.

Definition at line 1099 of file static_inst.cc.

References ArmISA::getRestoredITBits(), ArmISA::illegalExceptionReturn(), and ArmISA::unknownMode32().

Referenced by disabledFault().

◆ instSize()

ssize_t ArmISA::ArmStaticInst::instSize ( ) const

inline

Returns the byte size of current instruction.

Definition at line 521 of file static_inst.hh.

References StaticInst::machInst.

Referenced by encoding().

◆ isWFxTrapping()

bool ArmISA::ArmStaticInst::isWFxTrapping	(	ThreadContext *	tc,
		ExceptionLevel	targetEL,
		bool	isWfe
	)		const

inlineprotected

Definition at line 775 of file static_inst.cc.

References ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL1, and ThreadContext::readMiscReg().

Referenced by checkForWFxTrap32(), checkForWFxTrap64(), and disabledFault().

◆ printCCReg()

void ArmISA::ArmStaticInst::printCCReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 361 of file static_inst.cc.

References ccprintf(), and ArmISA::ccRegName.

Referenced by ArmStaticInst().

◆ printCondition()

void ArmISA::ArmStaticInst::printCondition	(	std::ostream &	os,
		unsigned	code,
		bool	noImplicit = `false`
	)		const

protected

◆ printDataInst() [1/2]

void ArmISA::ArmStaticInst::printDataInst	(	std::ostream &	os,
		bool	withImm
	)		const

protected

Referenced by ArmStaticInst(), ArmISA::DataXImmOp::generateDisassembly(), ArmISA::DataXSRegOp::generateDisassembly(), ArmISA::DataXERegOp::generateDisassembly(), ArmISA::PredImmOp::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), ArmISA::DataImmOp::generateDisassembly(), ArmISA::DataRegOp::generateDisassembly(), and ArmISA::DataRegRegOp::generateDisassembly().

◆ printDataInst() [2/2]

void ArmISA::ArmStaticInst::printDataInst	(	std::ostream &	os,
		bool	withImm,
		bool	immShift,
		bool	s,
		IntRegIndex	rd,
		IntRegIndex	rn,
		IntRegIndex	rm,
		IntRegIndex	rs,
		uint32_t	shiftAmt,
		ArmShiftType	type,
		uint64_t	imm
	)		const

protected

Definition at line 589 of file static_inst.cc.

References ccprintf(), ArmISA::INTREG_ZERO, printIntReg(), printMnemonic(), and printShiftOperand().

◆ printExtendOperand()

void ArmISA::ArmStaticInst::printExtendOperand	(	bool	firstOperand,
		std::ostream &	os,
		IntRegIndex	rm,
		ArmExtendType	type,
		int64_t	shiftAmt
	)		const

protected

Definition at line 557 of file static_inst.cc.

References ccprintf(), printIntReg(), ArmISA::SXTB, ArmISA::SXTH, ArmISA::SXTW, ArmISA::SXTX, ArmISA::UXTB, ArmISA::UXTH, ArmISA::UXTW, and ArmISA::UXTX.

Referenced by ArmStaticInst(), and ArmISA::MicroIntRegXOp::generateDisassembly().

◆ printFloatReg()

void ArmISA::ArmStaticInst::printFloatReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 342 of file static_inst.cc.

References ccprintf().

◆ printIntReg()

void ArmISA::ArmStaticInst::printIntReg	(	std::ostream &	os,
		RegIndex	reg_idx,
		uint8_t	opWidth = `0`
	)		const

protected

Print a register name for disassembly given the unique dependence tag number (FP or int).

Definition at line 296 of file static_inst.cc.

References aarch64, ccprintf(), ArmISA::FramePointerReg, ArmISA::INTREG_SPX, ArmISA::INTREG_UREG0, ArmISA::INTREG_X31, intWidth, ArmISA::PCReg, ArmISA::ReturnAddressReg, and ArmISA::StackPointerReg.

◆ printMemSymbol()

void ArmISA::ArmStaticInst::printMemSymbol	(	std::ostream &	os,
		const SymbolTable *	symtab,
		const std::string &	prefix,
		const Addr	addr,
		const std::string &	suffix
	)		const

protected

Definition at line 476 of file static_inst.cc.

References ccprintf(), and SymbolTable::findNearestSymbol().

Referenced by ArmStaticInst().

◆ printMiscReg()

void ArmISA::ArmStaticInst::printMiscReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 367 of file static_inst.cc.

References ccprintf(), ArmISA::miscRegName, and ArmISA::NUM_MISCREGS.

Referenced by ArmStaticInst(), MrrcOp::generateDisassembly(), McrrOp::generateDisassembly(), MiscRegImmOp64::generateDisassembly(), MiscRegRegImmOp64::generateDisassembly(), RegMiscRegImmOp64::generateDisassembly(), MiscRegRegImmOp::generateDisassembly(), and RegMiscRegImmOp::generateDisassembly().

◆ printMnemonic()

void ArmISA::ArmStaticInst::printMnemonic	(	std::ostream &	os,
		const std::string &	suffix = `""`,
		bool	withPred = `true`,
		bool	withCond64 = `false`,
		ConditionCode	cond64 = `COND_UC`
	)		const

protected

Definition at line 374 of file static_inst.cc.

References aarch64, StaticInst::machInst, StaticInst::mnemonic, and printCondition().

◆ printPFflags()

void ArmISA::ArmStaticInst::printPFflags	(	std::ostream &	os,
		int	flag
	)		const

protected

Definition at line 331 of file static_inst.cc.

References ccprintf().

Referenced by ArmStaticInst().

◆ printShiftOperand()

void ArmISA::ArmStaticInst::printShiftOperand	(	std::ostream &	os,
		IntRegIndex	rm,
		bool	immShift,
		uint32_t	shiftAmt,
		IntRegIndex	rs,
		ArmShiftType	type
	)		const

protected

Definition at line 493 of file static_inst.cc.

References ArmISA::ASR, ArmISA::INTREG_ZERO, ArmISA::LSL, ArmISA::LSR, panic, printIntReg(), and ArmISA::ROR.

Referenced by ArmStaticInst(), RegImmRegShiftOp::generateDisassembly(), and printDataInst().

◆ printTarget()

void ArmISA::ArmStaticInst::printTarget	(	std::ostream &	os,
		Addr	target,
		const SymbolTable *	symtab
	)		const

protected

Definition at line 395 of file static_inst.cc.

References ccprintf(), and SymbolTable::findNearestSymbol().

Referenced by ArmStaticInst(), ArmISA::BranchImm::generateDisassembly(), ArmISA::BranchImm64::generateDisassembly(), ArmISA::BranchImmCond64::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), and ArmISA::BranchImmImmReg64::generateDisassembly().

◆ printVecPredReg()

void ArmISA::ArmStaticInst::printVecPredReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 355 of file static_inst.cc.

References ccprintf().

◆ printVecReg()

void ArmISA::ArmStaticInst::printVecReg	(	std::ostream &	os,
		RegIndex	reg_idx,
		bool	isSveVecReg = `false`
	)		const

protected

Definition at line 348 of file static_inst.cc.

References ccprintf().

◆ readPC()

static Addr ArmISA::ArmStaticInst::readPC ( ExecContext * xc )

inlinestaticprotected

Definition at line 299 of file static_inst.hh.

References ExecContext::pcState().

Referenced by softwareBreakpoint32().

◆ satInt()

static bool ArmISA::ArmStaticInst::satInt	(	int32_t &	res,
		int64_t	op,
		int	width
	)

inlinestaticprotected

Definition at line 98 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

◆ saturateOp()

template<int width>

static bool ArmISA::ArmStaticInst::saturateOp	(	int32_t &	res,
		int64_t	op1,
		int64_t	op2,
		bool	sub = `false`
	)

inlinestaticprotected

Definition at line 82 of file static_inst.hh.

References bits(), LL, and ArmISA::width.

◆ setAIWNextPC()

static void ArmISA::ArmStaticInst::setAIWNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 357 of file static_inst.hh.

References ExecContext::pcState().

◆ setIWNextPC()

static void ArmISA::ArmStaticInst::setIWNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 347 of file static_inst.hh.

References ExecContext::pcState().

◆ setNextPC()

static void ArmISA::ArmStaticInst::setNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 305 of file static_inst.hh.

References ExecContext::pcState().

◆ shift_carry_imm()

bool ArmISA::ArmStaticInst::shift_carry_imm	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 217 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

◆ shift_carry_rs()

bool ArmISA::ArmStaticInst::shift_carry_rs	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 257 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

◆ shift_rm_imm()

int32_t ArmISA::ArmStaticInst::shift_rm_imm	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 57 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

◆ shift_rm_rs()

int32_t ArmISA::ArmStaticInst::shift_rm_rs	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 177 of file static_inst.cc.

References ArmISA::ASR, X86ISA::base, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

◆ shiftReg64()

int64_t ArmISA::ArmStaticInst::shiftReg64	(	uint64_t	base,
		uint64_t	shiftAmt,
		ArmShiftType	type,
		uint8_t	width
	)		const

protected

Definition at line 92 of file static_inst.cc.

References ArmISA::ASR, X86ISA::base, bits(), ccprintf(), X86ISA::exit, intWidth, ArmISA::LSL, ArmISA::LSR, ArmISA::mask, ArmISA::ROR, and ArmISA::width.

◆ softwareBreakpoint32()

Fault ArmISA::ArmStaticInst::softwareBreakpoint32	(	ExecContext *	xc,
		uint16_t	imm
	)		const

protected

Trigger a Software Breakpoint.

See aarch32/exceptions/debug/AArch32.SoftwareBreakpoint in the ARM ARM psueodcode library.

Definition at line 630 of file static_inst.cc.

References ArmISA::ArmFault::DebugEvent, ArmISA::EL1, ArmISA::EL2, ArmISA::ELIs32(), ArmSystem::haveEL(), ArmISA::imm, ArmISA::inSecureState(), StaticInst::machInst, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_MDCR_EL2, ThreadContext::readMiscReg(), readPC(), and ExecContext::tcBase().

Referenced by disabledFault().

◆ spsrWriteByInstr()

static uint32_t ArmISA::ArmStaticInst::spsrWriteByInstr	(	uint32_t	spsr,
		uint32_t	val,
		uint8_t	byteMask,
		bool	affectState
	)

inlinestaticprotected

Definition at line 281 of file static_inst.hh.

References bits(), and ArmISA::mask.

◆ sveAccessTrap()

Fault ArmISA::ArmStaticInst::sveAccessTrap ( ExceptionLevel el ) const

protected

Trap an access to SVE registers due to access control bits.

Parameters

el	Target EL for the trap.

Definition at line 972 of file static_inst.cc.

References ArmISA::EC_TRAPPED_SVE, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, and panic.

Referenced by checkSveEnabled(), checkSveTrap(), and disabledFault().

◆ trapWFx()

Fault ArmISA::ArmStaticInst::trapWFx	(	ThreadContext *	tc,
		CPSR	cpsr,
		SCR	scr,
		bool	isWfe
	)		const

protected

WFE/WFI trapping helper function.

Definition at line 874 of file static_inst.cc.

References checkForWFxTrap32(), ArmISA::currEL(), ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmSystem::haveEL(), ArmISA::inSecureState(), and NoFault.

Referenced by disabledFault().

◆ undefinedFault32()

Fault ArmISA::ArmStaticInst::undefinedFault32	(	ThreadContext *	tc,
		ExceptionLevel	el
	)		const

protected

UNDEFINED behaviour in AArch32.

See aarch32/exceptions/traps/AArch32.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 933 of file static_inst.cc.

References ArmISA::EC_UNKNOWN, generalExceptionsToAArch64(), StaticInst::machInst, StaticInst::mnemonic, and undefinedFault64().

Referenced by checkSETENDEnabled(), and disabledFault().

◆ undefinedFault64()

Fault ArmISA::ArmStaticInst::undefinedFault64	(	ThreadContext *	tc,
		ExceptionLevel	el
	)		const

protected

UNDEFINED behaviour in AArch64.

See aarch64/exceptions/traps/AArch64.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 952 of file static_inst.cc.

References ArmISA::EC_UNKNOWN, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, NoFault, and panic.

Referenced by disabledFault(), and undefinedFault32().

◆ uSatInt()

static bool ArmISA::ArmStaticInst::uSatInt	(	int32_t &	res,
		int64_t	op,
		int	width
	)

inlinestaticprotected

Definition at line 131 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

◆ uSaturateOp()

template<int width>

static bool ArmISA::ArmStaticInst::uSaturateOp	(	uint32_t &	res,
		int64_t	op1,
		int64_t	op2,
		bool	sub = `false`
	)

inlinestaticprotected

Definition at line 115 of file static_inst.hh.

References LL, and ArmISA::width.

Member Data Documentation

◆ aarch64

bool ArmISA::ArmStaticInst::aarch64

protected

Definition at line 62 of file static_inst.hh.

Referenced by printIntReg(), and printMnemonic().

◆ intWidth

uint8_t ArmISA::ArmStaticInst::intWidth

protected

Definition at line 63 of file static_inst.hh.

Referenced by getIntWidth(), printIntReg(), and shiftReg64().

The documentation for this class was generated from the following files:

arch/arm/insts/static_inst.hh
arch/arm/insts/static_inst.cc

Public Member Functions

Static Public Member Functions

Protected Member Functions

Static Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ArmStaticInst()

Member Function Documentation

◆ advancePC()

◆ advSIMDFPAccessTrap64()

◆ annotateFault()

◆ asBytes()

◆ checkAdvSIMDOrFPEnabled32()

◆ checkForWFxTrap32()

◆ checkForWFxTrap64()

◆ checkFPAdvSIMDEnabled64()

◆ checkFPAdvSIMDTrap64()

◆ checkSETENDEnabled()

◆ checkSveEnabled()

◆ checkSveTrap()

◆ cpsrWriteByInstr()

◆ cSwap() [1/2]

◆ cSwap() [2/2]

◆ disabledFault()

◆ encoding()

◆ extendReg64()

◆ generalExceptionsToAArch64()

◆ generateDisassembly()

◆ getCurSveVecLen()

◆ getCurSveVecLenInBits()

◆ getCurSveVecLenInQWords()

◆ getIntWidth()

◆ getPSTATEFromPSR()

◆ instSize()

◆ isWFxTrapping()

◆ printCCReg()

◆ printCondition()

◆ printDataInst() [1/2]

◆ printDataInst() [2/2]

◆ printExtendOperand()

◆ printFloatReg()

◆ printIntReg()

◆ printMemSymbol()

◆ printMiscReg()

◆ printMnemonic()

◆ printPFflags()

◆ printShiftOperand()

◆ printTarget()

◆ printVecPredReg()

◆ printVecReg()

◆ readPC()

◆ satInt()

◆ saturateOp()

◆ setAIWNextPC()

◆ setIWNextPC()

◆ setNextPC()

◆ shift_carry_imm()

◆ shift_carry_rs()

◆ shift_rm_imm()

◆ shift_rm_rs()

◆ shiftReg64()

◆ softwareBreakpoint32()

◆ spsrWriteByInstr()

◆ sveAccessTrap()

◆ trapWFx()

◆ undefinedFault32()

◆ undefinedFault64()

◆ uSatInt()

◆ uSaturateOp()

Member Data Documentation

◆ aarch64

◆ intWidth